OneSpin Solutions

September 24, 2015
OneSpin HLS and formal verification

Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.
July 21, 2014
ADAS

When failure is not an option in automotive verification

The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
January 13, 2014
Formal verification aids RTL verification

Formal verification enables Agile RTL development

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:

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