Expert Insight Complexity drives smart reporting Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL. by Lisa Piper Video New Ascent IIV Automatic RTL Verification Software Release: Faster Debug
DVClub 19 Sept 2014 Shanghai ARM TechCon 1-2 October 2014 Santa Clara Design Solution Forum Japan 3 October 2014 Shin-Yokohama DVCon 2-5 March 2015 San Jose Design Automation Conference (DAC) 7-11 June 2015 San Francisco
Article A common methodology to manage X propagation in both design and verification The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. The sheer complexity and the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state translating into a […]
Article The challenge of clock-domain crossings – and some solutions Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis. Article Clock-domain and reset verification in the low-power design era The multiple clock domains on today’s SoCs create a hotbed for clock-domain crossing bugs […]
Real Talk Article When to retool the front-end design flow? In the back-end world of circuit net lists and layouts, the decision to retool is simpler as the move to a new silicon technology node typically dictates when to change. In front-end design, it is much harder to identify when key metrics are not being […]
