The challenge of clock-domain crossings – and some solutions
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Clock-domain and reset verification in the low-power design era
The multiple clock domains on today’s SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
New 2014 release of Meridian CDC meets challenge of billion-gate SoCs
Hierarchy provides a smarter approach to SoC CDC verification
by Sarath Kirihennedige