Making the DATE

By Chris Edwards |  No Comments  |  Posted: March 1, 2006
Topics/Categories: EDA - IC Implementation  |  Tags:

DATE 06 (March 6-10) is the ninth edition of the Design Automation and Test in Europe conference and the organizers have again received a record number of submissions, this year 834. This reflects the fact that today DATE is not merely a European conference but has become a well-known global event, receiving paper proposals and delegates from almost 50 countries in all five continents. It is now the world’s premier event in electronic system design.

This year’s conference features a technical program with 78 sessions covering the latest in system design and embedded software, IC design methodologies and EDA tool development, together with an exhibition where the leading EDA, silicon and intellectual property (IP) providers will present new products and services. One of the main strengths of the conference is the broad but high-quality coverage of design, design automation and test topics, from the system level (including PCB and FPGA) to the IC level. In addition, for the second year, a dedicated embedded software track is being offered to account for this area’s increasing importance. Compared with previous years, submissions in design, test and embedded software have grown significantly, illustrating a clear market trend towards a more holistic view of the design flow and a comprehensive system-level focus.


The week opens on Monday March 6, 2006 at the Munich ICM Messe with a series of 11 pre-conference tutorials. Three full-day tutorials will cover topics of great interest to industrial designers. The first tutorial will look at the domain of processor architecture, unveiling all the secrets of the Sony/IBM/Toshiba-developed CELL processor, a new silicon family for the broadband era. The second will focus on system-on chip design, considering and comparing new system-level methodologies by way of their application to a high-definition video codec. The third will cover the hot topic of design for manufacturability and reviews emerging methodologies that are expected to move into the mainstream from the 65nm node onwards.

The remaining eight pre-conference tutorials are half-day sessions, four in the morning and four in the afternoon. They will cover aspects related to system-level design, test and modeling. The main conference opens on Tuesday March 7, 2006 with two influential and well-respected keynote speakers. René Penning de Vries, chief technology officer of Philips Semiconductors, will talk about EDA challenges in the era of converging applications, and Walden Rhines, chairman and CEO of Mentor Graphics and also chairman of the EDA Consortium, will address the sociology of design and EDA.

After the keynotes, DATE will launch its System Design Records Initiative, across two separate sessions. These will present papers that have been selected by a dedicated committee as containing novel ideas and proofs of concept from actual system design experiences. They will detail records in terms of performance, power management, size, and innovation in applications, or other concrete advantages which can be gained in the design of state-of-the-art applications.


DATE 06 is once again at the ICM Messe Munich

The designs being considered under the initiative are embedded or integrated systems, including systems-on-chip, systems-inpackage, and FPGA-based or reconfigurable platforms, up to large boards.

Following its success in previous years, the full-day Executive Track will also return on Tuesday with a full range of presentations from CEOs, CTOs, vice presidents and other senior executives at leading CAD vendors, IP suppliers, semiconductor companies and systems houses.

On Wednesday March 8, 2006, a special full-day track has been devoted to 4G Telecommunication Applications and Design. The telecommunications and semiconductor industries are inseparably linked. More than 60% of chip company revenues now come from communications and multimedia applications. At the same time, the demand for ultra-high computational performance from the wireless and multimedia spaces has become a core technology driver for the silicon business.

The need to prepare cellular 4G solutions is today self-evident. In that context, the single most important aspect of designing and, successfully deploying 4G, is its cross-disciplinary character, ranging from semiconductors to services to deployment to business models. During the DATE focus day, the various issues involved in defining, designing, and deploying 4G will be addressed, with particular attention paid to the system-level design of complex SoCs.

On Thursday March 9, 2006 a second special full-day track focuses on wireless sensor networks. This is a trend that has been gathering pace during the last few years. Such networks involve the deployment of a large number of small low-cost nodes, which can sense environmental changes and report them to other nodes over a flexible network architecture. Sensor nodes are excellent for deployment in hostile environments or over large geographical areas, and they have already been effectively used in such different application domains as environmental observation, military monitoring, building monitoring and health care. However, due to their small size, the sensors do still have many limitations.

This special track will focus on the main issues involved in the design of such sensor networks, covering factors such as identifying the appropriate hardware platforms for sensor nodes to address resource limitations (e.g., low power, limited memory, small size). In addition, the track will consider the associated power communication issues; look at how to achieve the kind of distributed data processing that can handle data coming from many different sensors and fuse it into useful results; and review today’s applications and open research findings.

The main DATE conference program has been organized in six parallel tracks. Three are devoted to tools and methodologies for the design of electronic systems from system-level down to manufacturing. One is dedicated to test issues. One takes a specific view of issues facing designers in terms of applications, tools and architectures through real industrial design demonstrations. And one is dedicated to embedded software.

The original 834 submissions have been reviewed by over 350 experts and 270 papers have been selected for presentation in Munich. New this year are sessions on the expansion in architectures and micro-architecture design, an increased and stronger program on system-level methodologies and tools, and a broader range of papers covering low-power solutions. In fact, 35% of the sessions in the main conference program relates to embedded systems design methods, architectures and software. A further 17% is on test issues; 15% relates to digital design methodologies and tools; 10% covers low power techniques; 8% is on analog system design; and 15% focuses on design applications. Novel ideas will be presented in specific Interactive Presentation sessions.

Seven special sessions complement the main conference program, including embedded tutorials, highlights on hot topics, and panels on the most interesting issues now facing electronic design. In particular, communication-based design is the topic of two special sessions: one on the design challenges, the other on automotive applications.

Automotive microelectronics is also the focus of a special session that will analyze test and reliability challenges, and possible solutions based on the practical experience of representatives from the motor industry.

New methodologies and their industrial application to design for manufacturability and design for yield strategies will be considered in an embedded tutorial followed by a discussion panel.

Power consumption remains one of the ‘hot-button’ topics in research and an embedded tutorial will first review the stateof- the-art in design technologies for dynamic and leakage power minimization. It will then move on to a public ‘trial’, in which OEMs, IDMs, IP and fabless semiconductor vendors will play the role of the public prosecutor against the tool vendors to judge whether or not the EDA industry is taking low-power matters sufficiently seriously, and what should be the near-future targets. Finally, a system-level embedded tutorial on model-based design will demonstrate the application of Simulink, Matlab and UML in the design of embedded systems.

Friday March 10 is primarily dedicated to the DATE Workshops, offered as a further complement to the regular conference. Five workshops will run in parallel, covering emerging and important design topics such as FPGA-based computing; future trends in automotive electronics; design issues in communication-centric systems; interconnects and networks on chip; and CAD tools for biochips. Each workshop will feature presentations from highly distinguished academic and industrial researchers.

Finally, throughout the conference, the DATE Exhibition will be open to designers. More than 100 exhibitors include the leading EDA, silicon, FPGA and IP providers. In addition, the Exhibition Theatre will feature engineering managers from leading electronic manufacturers talking about their personal design experiences with commercial EDA tools.

This year, the exhibition program includes Designers’ Solutions Workshops, short training sessions organized by vendors on specific topics such as SystemVerilog, SystemC, verification and FPGA design. On Thursday March 9, as part of the exhibition program, the PCB Symposium will take place in parallel to the main conference. The focus this year will be on the integration of FPGAs/ICs with PCBs in system designs.

DATE week will also provide an opportunity for students and universities to present their research at the PhD Forum on Monday and at the University Booth in the exhibition, where hardware and software demonstrations from numerous institutions will take place on a rotating schedule.

The DATE 06 event’s program will be particularly attractive to industrial designers, at IC, FPGA and embedded system levels, and to researchers and academics as well as to design managers.

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