Dresden’s designs on DATE

By Paul Dempsey |  No Comments  |  Posted: April 14, 2010
Topics/Categories: EDA - ESL  |  Tags:  | Organizations:

Europe’s premier EDA conference moves to Silicon Saxony

The 12th edition of Design Automation & Test in Europe (DATE) takes place March 8-12 in Dresden, Germany. As ever, the conference program shows DATE targeting some of the most pressing issues in electronic design with a particular emphasis on ESL and embedded software.

The conference will take place in Dresden’s International Congress Center and is the second major European event to move to ‘Silicon Saxony’ in the last few months. Semicon Europa was held in the city last fall and will return in October 2010. The region claims to be the world’s fifth largest cluster for electronics and many of its key players are participating in the exhibition that runs alongside the main technical sessions.

DATE’s line-up of technical papers was drawn from a record number of submissions, just below 1,000. Alongside material to catch the specific interests of conference delegates, it is also hosting a wide range of panels and two Special Days, which we will preview in a little more detail. Information on how to access the DATE program in full appears at the end of the article.

Keynote Speakers

There are four well-known keynote speakers on this year’s program, addressing topics such as system design, wireless communications and nanoelectronics. Alberto Sangiovanni-Vincentelli, the Buttner Professor of Electrical Engineering and Computer Sciences at UC Berkeley and a board director of Cadence Design Systems, will deliver one of the two addresses that open DATE, “All Things Are Connected” (Tuesday, 9th March, 9.10am, Grosser

 Saal), concentrating on the interdependencies within designs and how these need to be reflected in the industry’s processes and methodologies.

“There is increasingly less distance between design and operation of systems. An efficient management of interactions among deployed parts of a larger system requires principles that are common to the design methods developed at the bleeding edge of technology,” he says.

“I will examine the evolution of design principles and of multiscale systems and the challenges we are facing today. I will point to a number of exciting fields where advances are constantly made toward the mastering of connections.”

The second opening keynote will be by Herman Eul, executive vice president of Infineon Technologies for Sales, Marketing, Technology and R&D, and is entitled “Wireless Communication: Successful Differentiation on Standard Technology by Innovation” (Tuesday, 9th March, 9.50am, Grosser Saal).

His focus will be on how chip companies can most effectively add value to their efforts in this arena as we move to a point where as much as three quarters of the world’s population is using cellular devices as their primary way to access information and also games, media and social networks.

“In the highly competitive mobile phone market, growth depends on differentiation by innovation,” he says. “This requires technology know-how being effectively transferred into the design system and application-specific device structures to create optimized circuits.”

Two other keynotes accompany DATE’s Special Days on Cool Electronic Systems and Nanoelectronics. First, Mark Horowitz, director of the Computer Systems Laboratory at Stanford University, will consider some of the methodological questions raised by the earlier speakers in his address, “Why Design Must Change: Rethinking Digital Design” (Wednesday, 10th March, 2pm, Saal 5). Part of the Cool Electronic Systems strand, Horowitz’s speech will take a radical and provocative stance. “I don’t believe that either the current SoC [system-on-chip] or high-level language effort will succeed,” he says.

“Instead, we should acknowledge that working out the interactions in a complex design is complex, and will cost a lot of money even when we do it well. The key is to leverage this work over a broader class of chips. This approach leads to the idea of building chip-generators and not chips. That is, instead of building a programmable chip to meet a broad class of application needs, you create a virtual programmable chip that is much more flexible than any real chip.”

Horowitz believes that some companies are already using such techniques—“like letting the generator choose the core that is the most energy efficient for your application mix”—and will provide several examples.

For the Nanoelectronics strand, keynote speaker Dimitris Antoniadis, professor in the Microsystems Technology Laboratory at the Massachusetts Institute of Technology, will tackle the debate over architecture, materials science and physical limitations that has been raging ever since it became obvious that traditional scaling is coming to an end.

“Nanoelectronics Challenges for the 21st Century” (Thursday, 11th March, 1.30pm, Saal 5) will review the various alternatives from III-V materials through to more recent proposals such as carbon nanotubes and graphene.

“Of course, declaring silicon dead is premature at best,” he counsels. “And with this in mind, I will discuss the challenges and possible scenarios for the introduction of novel nanoelectronic devices.”

Executive Sessions

The Executive Sessions at DATE pull out key challenges facing the industry as a whole. Given that Dresden is also home to the flagship fab of the recently created Globalfoundries group (it was formerly AMD’s main site in Europe), it is appropriate that two of the three sessions at the 2010 event should address aspects of design for manufacturability (DFM). Both 90-minute sessions take place back-to-back on Tuesday, 10th March in Saal 5.

First, “The Impact of Nanometer Technologies on Yield” (2.30pm) will seek to identify “advanced optimization solutions” with panelists from AMD, Intellitech, Globalfoundries, Mentor Graphics, Open Silicon and Texas Instruments.

Then, “Impacts of Continuous Scaling on the Semiconductor Industry” (5pm) will address the effect of sub-28nm issues on development flows generally with panelists from Abu Dhabi’s Advanced Technology Investment Company (parent of Globalfoundries), eSilicon, Taiwan’s Industrial Technology Research Institute, TSMC and Virage Logic.

A further Executive Session, also in Saal 5 on Tuesday, will consider DATE’s traditionally strong subject of ESL. “How to Address Today’s Growing System Complexity” (11.30am) will be moderated by analyst Gary Smith and feature panelists from Aspex Semiconductor, IBM, Infineon Technologies, Intel, Numetrics and Synopsys.

Special Days

Alongside the main technical program, DATE regularly offers sessions clustered around specific topics or areas of growing interest. In 2010, Wednesday has one such strand on Cool Electronic Systems, which brings together challenges in both wireless communications and reducing power consumption. The title also reflects Silicon Saxony’s regional initiative on “Cool Silicon.”

In addition to the keynote cited above, the day is made up of a panel and three paper sessions. The panel, “The Road to Energy-Efficient Systems: From Hardware-Driven to Software-Defined” (8.30am, 10th March, Saal 5), will address one of the fundamental trends in all system design today with speakers from academia and industry.

The three paper sessions will then consider sensor networks (11am), communications systems (2.30pm) and computing platforms (5pm). Companies discussing their technical research in these areas include Vodafone, ARM, the Fraunhofer Research Institute and Tensilica.

Thursday’s Special Day strand is Nanoelectronics. This starts in the morning with two tutorials, “More Moore and Beyond CMOS” (11th March, 8.30am, Saal 5) and “More than Moore” (11.00am, Saal 5), which both expose big picture issues, such as variability, and drill down into specific materials being proposed for the ‘post-silicon’ era, such as organic electronics.

After the lunchtime keynote, a paper session, “Life With and After CMOS” (2pm, Saal 5), presents research from the powerful troika of Intel/SRC, Fraunhofer and IBM, and then a panel session includes speaker Antoniadis with representatives from IMEC, Intel, CEA-LETI and Lund University on the topic “Great Challenges in Nanoelectronics and the Impact on Academic Research” (4pm, Saal 5).

Exhibition Theater Panels

In parallel to the main conference, there is also a series of panel sessions held in DATE’s Exhibition Theater that are open to all attendees, and located alongside the stands on the ground floor of the conference center. This year, three of these panels are particularly worth highlighting.

Two of these look at challenges in the embedded space. “Who Is Closing the Embedded Software Gap?” (Wednesday, 10th March, 2.30pm) looks at the difficulties now arising as software complexity in HDL and C rises at a faster rate than that of the silicon hardware. Representatives from EDA vendors Synopsys and Mentor, as well as Infineon, Bosch, Siemens and UC Irvine, will look at how new tools are meeting industry’s needs.

Then, “Embedded Software Testing: What Kind of Problem Is This?” (Thursday, 11th March, 8.30am) looks at an area that is also pushing its way up the agenda not only because of increasing code complexity, but also as engineers seek to finesse the differences between traditional software and that used in embedded systems. Contributors here will represent CoWare, IBM, IMEC, Research & Consulting, Verona University and Tensilica.

Meanwhile, another Thursday panel aims to address an area that has been knocking on the door seeking attention for several years, but which the immediate challenge of nanometer DFM has hitherto tended to drown out—“Lots of Foundries and Fabless Companies Do Exist—What About Standards for Their Interface?” Panelists here will offer views from Atmel, IPGEN, LANTIG, X-Fab and Globalfoundries.

The above are very much edited highlights from the DATE program, which actually offers far greater depth and addresses specific technical challenges. They are, in short, events you may wish to attend as a side order to the main course. To see all that is on offer, visit the conference website.

All details and venues were correct at the time of going to press, but please also check the up-to-date conference agenda for the sessions mentioned here and others, www.date-conference.com.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors