Active power management for configurable processors

By Brian Knowles |  No Comments  |  Posted: March 1, 2008
Topics/Categories: EDA - Verification  |  Tags:

ARC International is one of the largest suppliers of configurable processor technology. It licenses patented configurable multimedia subsystems and CPU/DSP processors that are used to design differentiated products. They are optimized for use in systemson- chip (SoCs) that consume less power, are less expensive to produce and require protection from cloning.

The ARC Energy PRO flow presented here is a new technology for active power management. It can reduce the power requirement by as much as 4X and is based on the integration of hardware, software and EDA design processes. It is primarily aimed at applications for battery-operated portable devices in markets such asWiMAX, digital radio, medical devices, etc.

The flow described in this article is based on the Common Power Format (CPF). Translators that enable analogous strategies to be adopted using the Unified Power Format (UPF) will be available in due course.

The power struggle

Traditional low power design challenges have included increasing functionality,minimizing the cost of packaging and cooling, and improving reliability. However, the emerging and increasingly important low power design challenge is the extension of battery life.

In the last three decades, SoC computational power has increased by more than four orders of magnitude, while battery capacity has increased by only about 4X. This trend is likely to continue. The main response to this must be to address power across all phases of the product design with flows that are specifically tuned for this issue, such as the Common Power Format (CPF) and the Unified Power Format (UPF).

This article discusses the ARC Energy PRO flow (Figure 1), which has been optimized for the configurable cores and subsystems supplied by ARC International. These cores are widely used today in a range of portable devices with stringent low power requirements. As discussed here, the flow illustrated is based around CPF, although a UPF version will also be made available.


Figure 1. Full ARC Energy PRO design flow

Power management techniques

Configurability and extensibility are key factors in serving markets such as wireless communications, networking, consumer electronics, multimedia and storage. The design configuration for each target application must achieve both minimum design size (with no wastage in the silicon footprint), and the lowest power design (with no inactive functional blocks). The goals for extensibility are that it should be easy for designers to add specialized functions to the end-product and that they should have more opportunities to contribute further features that allow for the greatest viable product differentiation.

The power management options in Energy PRO that address these challenges include traditional techniques such as fine-grain clock gating and user-driven multiple threshold voltage (Vt) optimization; but there are also advanced techniques to control power consumption in both the active and inactive modes of the product’s operation. These can be summarized as follows:

For inactive modes and blocks, the flow will:

  • Target power reduction when a device is on ‘standby’ for long periods;
  • Address situations where there may be high latency on ‘restart’;
  • Gate the clocks at the highest possible level; and
  • Power down the core of the design.

During active modes, the flow will:

  • Target power reduction when operational;
  • Address potential impacts on functionality;
  • Address potential impacts on functional latency;
  • Gate the clocks for a function when it is not in use; and
  • Reduce the voltage and frequency for non-compute intensive operations.

Coordinated power management for the ARC-based components of an SoC design also provides an interface for extending the techniques used to the rest of the SoC.

Energy PRO software components

Key features of Energy PRO, such as switching power modes and dynamic voltage and frequency scaling (DVFS), are invoked under software control. As a result, the ARCompact instruction set architecture (ISA) has been enhanced to support the new flow. ARC provides software APIs that give access to Energy PRO features and that can be used by both the operating system and by applications directly.


Figure 2. ARC CPU with co-processor subsystem

Figure 3. Power intent – power shutoff

An Energy PRO-aware version of the MQX RTOS is now available. This provides an applications interface to Energy PRO. It records power management activity. Also, it can intelligently optimize appropriate settings for power based on thread requirements and the workload profile.

Energy PRO design flow

Simple low-power techniques can be incorporated at discrete points in the Energy PRO design flow. These include fine-grain clock gating during synthesis and multi-Vt optimization during synthesis and/or layout. Advanced techniques are complex and affect multiple tools throughout the design flow. This is where integration with a standard such as CPF is of critical importance, as it enables the following and other techniques to be used:

  • Accurate simulation of power down modes;
  • Insertion of isolation cells and level shifters during synthesis;
  • Timing optimization with special power cells;
  • Placement of voltage regions and cells into the correct regions; and
  • Verification of the power intent.

ARC partnered with Cadence Design Systems and Virage Logic to develop the low power reference flow based on CPF which includes such advanced features. Objectives for the project were:

  • By using a sample design, to capture the power intent in the form of a CPF file;
  • To develop a low power reference flow for the sample design;
  • To make the power intent data configurable across ARC processor cores; and
  • To make the design flow configurable for use with ARC cores.

Figure 4. Below 180nm, systematic feature-related yield loss becomes a critical issue


Figure 5 Below 180nm, systematic feature-related yield loss becomes a critical issue

Project subsystem: ARC CPU with co-processor

The project subsystem was an ARC CPU with a co-processor that could process large data streams. There were seven functional blocks as shown in Figure 2. This diagram also shows the four different domains for clock gating power management.

When processing high bit-rate data streams, both the ARC CPU and the co-processor run flat out for high performance.When processing a lower bit-rate data stream, the subsystem can be run at a lower frequency. For generic processing, the coprocessor can be inactive.

This architecture lends itself to several advanced power management techniques, including power shutoff (PSO or power gating) and voltage scaling (DVS).

Power intent: power shutoff

First, let’s explore PSO and its architecture. Figure 3 shows the two different power domains (‘CORE’ and ‘SIMD’) relevant to PSO, with control signals, power switches and isolation. Note that a new block of always-on logic has been defined for a total of eight blocks.

The three modes of operation, ‘PDOS’, ‘PDO’ and ‘PD2’ combined with the two power domains are summarized in the table shown at the bottom of Figure 3.

Power intent: dynamic voltage scaling

Dynamic voltage scaling adds complexity. It introduces two differently defined power domains appropriate for DVFS as shown in Figure 4. The three performance modes, with associated voltages and their control signals, are shown in the table on the left of Figure 4. The table to the right shows, by mode of operation or performance mode, what is the status of the two switched power domains ‘RAM’ and ‘CORE’.

Power intent: combined

Combining the two power management techniques, we see from Figure 5 that there are now four power domains, layering four clock gating domains, defined for the eight blocks in the system. The tables in Figure 5 describe the voltage levels, the switched power domains, and the modedependent behavior of the low power architecture.

Power savings


Figure 6. Below 180nm, systematic feature-related yield loss becomes a critical issue

The tables in Figure 6 (p.28) summarize the benefits of the low power architecture. Power saved by DVFS during low bit-rate data streams vs high bit-rate data streams is over 50%; DVFS offers savings of almost 50% for generic processing at high and lower frequencies. PSO or power gating could potentially lead to even greater savings – depending on the end-design application – during standby, wait and other power-down modes.

Design flow implications

Clearly, if results of this quality are to be achieved, the power intent of the design needs to be clearly understood throughout all the design flow stages. For this example, CPF-enabled design tools were central to achieving this at design stages such as RTL simulation, power analysis, synthesis, formal verification, and place & route.

Design and verification with a format such as CPF or UPF identifies and prevents challenging problems emerging when the engineer wants to use techniques such as isolation cells and level shifting. During clock gating, a power-aware flow ensures that powered-down blocks no longer receive a clock signal. And to prevent rogue RTL, when a signal goes from one module to another, it ensures that there are no ‘simple’ operations happening in an un-powered domain.

Reference design flow

ARC has now released a design flow for the new cores, wherein CPF describes the power intent and ensures consistent implementation across all tools in the design flow (Figure 7). As noted above, it is our intention that similar capabilities should also be available in the future for UPF.


Figure 7. Below 180nm, systematic feature-related yield loss becomes a critical issue

In the CPF flow, ARChitect configures the design in the context of the Cadence flow and library data, including specialist low power cells, which have been supplied by Virage Logic.


ARC Energy PRO represents a new active power management technology that reduces power by as much as four-fold. Its endto- end fully verified power management solution reduces time-tomarket for advanced SoC designs and is ideal for battery-operated portable applications. This Energy PRO technology will be included in future ARC processor cores and multimedia subsystems spanning a breadth of design applications and markets.

ARC International
3590 N. First Street, Suite 200
San Jose CA 95134

T: +1 408 437 3400

Point StationWay
St Albans

T: +44 (0)1727 891400

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