The quest for denser IC processes operating at lower power has seen a steady reduction in supply voltages, which cuts both static and dynamic energy consumption. Operating at near-threshold or sub-threshold voltages reduces this further, at the cost of having to overcome a number of circuit design and characterisation challenges.<\/p>\n
To recap, a transistor\u2019s threshold voltage (Vth) is the voltage at which the transistor turns on. Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise.<\/p>\n
In sub-threshold operation, as shown in Figure 1, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned On. In today\u2019s process technologies, this region is at about 200 \u2013 400mV.<\/p>\n
Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 \u2013 700mV for today\u2019s processes.<\/p>\nNo URL for image<\/em>\n Static power consumption scales down linearly with the reducing supply voltage, but dynamic power consumption scales down much quickly in proportion to the square of the supply voltage.<\/p>\n Sub-threshold transistor operation is not new, but working with the techniques has challenges that have prevented it from being widely applied.<\/p>\n One such challenge is working out how much the supply voltage can be reduced before the leakage current dominates the dynamic (switching) current. Figure 2 shows that dynamic power continues to drop as the supply voltage is lowered, but process-driven leakage currents start to rise. The trick to using sub-threshold techniques effectively is to find the supply voltage at which the combination of leakage and dynamic power reaches its minimum.<\/p>\n No URL for image<\/em><\/em><\/p>\n Sub-threshold circuits are much more sensitive to noise than those operating at higher supply voltages, with noise margins that are several orders of magnitude less. Typical super-threshold designs will see noise margins of hundreds of mV, which can drop to less than 100mV in a sub-threshold design. Standard-cell developers must try to design cells that claw back some of this loss of noise margin (NMH and NML in Figure 3).<\/p>\n No URL for image<\/em>\u00a0<\/em><\/p>\n Process and temperature variations are also more critical in sub-threshold designs as these can cause significant yield and performance problems.<\/p>\n Since most foundries\u2019 standard-cell libraries are optimized to operate with supplies of ~0.9V (+\/- 20%), their transistor models tend not to be accurate at sub-threshold voltages. Many IC vendors who want to use sub-threshold techniques are building their own standard-cell, memory and analog circuit libraries, which they can be sure are properly characterised at these challenging operating conditions.\u00a0<\/strong><\/p>\n A few IC vendors are starting to use near\/sub-threshold techniques, especially in battery-operated applications such as the IoT. Synopsys and PLSense (South Yokneam, Israel) have worked together to implement Synopsys\u2019 ARC processors and subsystems using PLSense\u2019s sub-threshold libraries and design techniques, to understand the potential systemic energy savings.<\/p>\n No URL for image<\/em><\/em>\u00a0<\/em><\/p>\n The PLS10 IC operates between 0.45V and 1.1V from a battery. An adaptive dynamic voltage control algorithm adjusts the operating voltage to achieve the required clock frequency.<\/p>\n PLSense\u2019s designed its sub-threshold cell library to minimise the voltage variance between the \u201cfast NMOS\/slow PMOS\u201d (FS) and \u201cslow NMOS\/fast PMOS\u201d (SF) process corners (Figure 5). It was also able to improve the noise margins for these corners (Figure 6), compared to standard foundry libraries.<\/p>\n No URL for image<\/em><\/em><\/p>\n \u00a0No URL for image<\/em><\/em><\/p>\n Using benchmarks such as EEMBC CoreMark, PLSense claims its approach offers up to nine times lower power consumption (measured in mA\/MHz) than competitive low-power ICs, including other near\/sub-threshold MCU designs (Figure 7).<\/p>\n No URL for image<\/em><\/em><\/p>\n Operating with near-threshold or sub-threshold supply voltages can cut power consumption, at the cost of having to develop cell libraries and design methodologies that can overcome some of the technique\u2019s limitations, such as susceptibility to noise and process variations. However, in markets such as IoT devices, where every Joule of energy saved means a few more minutes on the battery life, it may well be worthwhile.<\/p>\n <\/p>\n Case Study: PLSense achieves 0.45V operation with sub-threshold technology implemented<\/a>\u00a0on Synopsys\u2019 ARC Data Fusion IP subsystem<\/a><\/p>\n Webinar: Techniques to accelerate data fusion in your SoC: high-performance sensor, voice and audio processing<\/a><\/p>\n Rich Collins is a product marketing manager at Synopsys.<\/p>\n Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.<\/p>\n","protected":false},"author":329,"featured_media":9515,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1242],"tags":[1551,2068,1552],"coauthors":[996],"class_list":["post-9503","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-architecture-design","tag-near-threshold-logic","tag-noise-margin","tag-subthreshold-logic","workflow-case-study","workflow-front-lead","workflow-technique","workflow-up-to-date","organization-synopsys"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/9503","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/329"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=9503"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/9503\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media\/9515"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=9503"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=9503"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=9503"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=9503"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}The challenges of using sub-threshold technology <\/strong><\/h2>\n
Bringing sub-threshold designs to market <\/strong><\/h2>\n
Conclusion <\/strong><\/h2>\n
Further information<\/b><\/h2>\n
Author<\/b><\/h2>\n
Company info<\/b><\/h2>\nSynopsys Corporate Headquarters<\/i><\/address>\n 690 East Middlefield Road<\/i><\/address>\nMountain View, CA 94043<\/i><\/address>\n(650) 584-5000<\/i><\/address>\n(800) 541-7737<\/i><\/address>\n\u00a0<\/i>www.synopsys.com<\/a><\/i><\/address>\n","protected":false},"excerpt":{"rendered":"