Up to now, timing signoff for implementation flows has been based on advanced on-chip variability (AOCV) techniques that attempt to close the gap between real-world variability effects and the ability of the traditional design flow to estimate their effect on logic timing.<\/p>\n
Ruben Molina, product marketing director for signoff at Cadence, says: \u201cYou can always take a process node and apply enough margin to cover the variation, but today, you are really going to suffer from a performance standpoint with that methodology. You have to add so much margin now, that it offsets the performance advantage of advanced process nodes, and no-one wants to do that when mask costs are such a huge investment. They want to squeeze out as much performance as they can to take full advantage of the latest technologies.\u201d<\/p>\n
The migration to 10nm will include a shift towards the adoption of the more advanced statistical method: SOCV. A number of factors have come together to drive the shift to SOCV, including the earlier engagement of the foundries in characterizing processes, the greater need for low-power IC design, and the arrival of standard ways of representing the data.<\/p>\n
\u201cOne thing that makes this more of a reality at 10nm is the release of the Liberty variation format (LVF) which consists of a set of new variables that are added to the libraries that model the statistical delay based on process variation,\u201d says Molina. \u201cLVF shouldn\u2019t be confused with a brand or a vendor specific methodology: it\u2019s simply a format to represent these statistical variables in a library.\u201d<\/p>\n
The LVF data is used by tools such as the Cadence Tempus Timing Signoff Solution to calculate how variability for each cell in a path is likely to affect its timing \u2013 something that gets worse as supply voltages reduce.<\/p>\n
\u201cOne thing that is increasing variability is ultralow voltage operation. Even at 16 and 14 nm, we are seeing library variants where the main operational voltage is very close to the switching threshold. These are conditions where you will see a lot more variation because currents are smaller and outputs don\u2019t switch until the input waveforms are in the tail region. Thus, delay variation increases as a result of all of these factors. The bottom line is that ultralow voltage operation is contributing to the overall variability situation,\u201d Molina says.<\/p>\n
The issue that faces AOCV in this environment is that the simplifications used to make it easier to compute for large SoCs leaves too much performance on the table through excessive guard banding. AOCV improves on traditional OCV techniques because it takes account of some statistical variability effects, using tables that allow each stage of logic in a path to affect the path\u2019s overall derating.<\/p>\n
AOCV reduces the level of derating for each stage on the basis that each successive stage will cancel out the variation. \u201cSome stages will be faster; others slower. So the more stages you have, the more it averages out,\u201d says Molina. \u201cThe problem with purely stage-based variation is that the timing of actual cells in path have dependencies on the slews and loads they see. But AOCV only accounts for variation based on the number of stage and for a single kind of gate, such as an AND gate.\u201d<\/p>\n
The source gate used to generate the stage-based tables will be generated based on extensive Monte Carlo simulations, but such an approach cannot take account of the large potential differences in behavior of the actual gates in the path. A path comprised of comparatively complex gates is likely to behave differently to one based on a longer sequence of simple gates.<\/p>\n
\u201cAnother variable that isn\u2019t captured by AOCV is slew variation, particularly at low voltage. You don\u2019t see only a delay sigma [deviation] but a sigma for slew and for the setup and hold constraints. Slews have an impact not only on delay through the cell but the output slew as well. And the output slew is also highly dependent on the load,\u201d Molina adds. \u201cIn SOCV, these things are all needed to model the delay through the cells accurately.\u201d<\/p>\n
The libraries needed for SOCV will be delivered by the foundries in the form of LVF data for the timing-closure tools and fit into a methodology similar to that employed today.<\/p>\n
\u201cSOCV is not a huge hit on runtime, which makes it very appealing,\u201d says Molina.<\/p>\n
There are other aspects of design that will allow SoC designers to take more margin out of the equation, according to Molina: \u201cAnother key modeling question is what to do about interconnect variation. When we utilize parasitic extraction information for delay calculation, we typically assume that the metal is a given width and that there isn\u2019t going to be variation for a parasitic process corner. But there is. And that will need to be modeled.\u201d<\/p>\n
The concept was introduced when much more CPU-intensive statistical methods were mooted that looked at all critical dimensions around the transistor. To some extent, this variation can be handled through simulation of best-worse resistance and capacitance corners. \u201cAlso within one of those corners will be additional variation. We need to figure out the best way to handle that without making it too heavyweight a process,\u201d Molina says.<\/p>\n
Systematic variation represents a further dimension in signoff as the location of cells relative to each other on the die will affect their parameters \u2013 with less variation exhibited by cells that are close together. \u201cThe statistical methods are there primarily to cover the random process effects not systematic based variations due to things like metal density across the die. But there are ways to merge that information with the statistical methods. It\u2019s now fairly well understood and is something handled even going back to stage-based OCV. Systematic variation adds a second dimension.<\/p>\n
\u201cWith SOCV analysis we can have a derate applied as well that is based on where the cells are located: which bounding box are they are contained within,\u201d Molina says.<\/p>\n
How the systematic effects are factored into the analysis is largely a matter of choice by the design team, trading off risk, performance, and accuracy.<\/p>\n
Molina adds: \u201cThe other two variables are the voltage variation and the temperature variation. Those are the other two components that have a huge impact on the delay. We are working on ways to include voltage and temperature variation in the approach.\u201d<\/p>\n
The result is that the push for performance at low power at 10nm will see changes in timing signoff. But the industry is readying the toolkit to make it possible.<\/p>\n","protected":false},"excerpt":{"rendered":"
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.<\/p>\n","protected":false},"author":327,"featured_media":8444,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[38,35],"tags":[1473,1537,1420,1817,1416,1422,1540],"coauthors":[993],"class_list":["post-8442","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ic-implementation","category-design-verification","tag-10nm","tag-14nm16nm","tag-aocv","tag-socv","tag-static-timing-analysis","tag-timing-closure","tag-variability","workflow-featured","workflow-front-lead","organization-cadence-design-systems"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/8442","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/327"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=8442"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/8442\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media\/8444"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=8442"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=8442"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=8442"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=8442"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}