{"id":8394,"date":"2015-12-09T08:56:40","date_gmt":"2015-12-09T08:56:40","guid":{"rendered":"https:\/\/www.techdesignforums.com\/practice\/?p=8394"},"modified":"2015-12-10T00:35:00","modified_gmt":"2015-12-10T00:35:00","slug":"emulation-iot-networking-challenges","status":"publish","type":"post","link":"https:\/\/www.techdesignforums.com\/practice\/technique\/emulation-iot-networking-challenges\/","title":{"rendered":"Emulation overcomes the five main IoT and networking verification challenges"},"content":{"rendered":"

Massive verification is needed to design the products and networks that make up the Internet of Things (IoT) and networking ecosystem. These are large, complex designs. They feature huge amounts\u00a0of software and must meet stringent low power requirements. As such, they require an enormous number of verification cycles to fully exercise and debug.<\/p>\n

Five characteristics of IoT and network designs have most impact on the verification task. Four are common to both: more protocols per chip, larger and more complex designs, lower power usage requirements, and more software. Networking systems then add a fifth challenge: the growing number of switch and router ports.<\/p>\n

\"The<\/a>

Figure 1. The top four hazards facing IoT design (Mentor Graphics)<\/p><\/div>\n

Only emulation has the capacity, speed, and capabilities that allow you to complete so much verification efficiently. Yet we also need to think carefully about how emulation itself should now be used. Traditional in-circuit emulation (ICE) cannot accommodate the exploding number of Ethernet ports that networking companies use in their systems. Nor is it practical for testing the multitude of interface protocols found on IoT devices.<\/p>\n

We need to move beyond traditional ICE toward software-centric, virtual emulation.<\/p>\n

First we\u2019ll look at the challenges, then their solutions.<\/p>\n

Primary challenges of IoT and networking designs<\/h3>\n

1. More protocols per chip <\/strong><\/h4>\n

Because more applications and functions need to connect to a network at the same time, the number of protocols-per-device is increasing. For example, mobile phones need to connect to storage on the cloud, stream video and audio, run various kinds of app, and send and receive phone calls and texts.<\/p>\n

The protocols needed to do all this can be complex in themselves. But because there is so much communication and so many interactions between the different protocols and the rest of the design, they generate\u00a0a lot of different tricky scenarios and corner cases that need to be checked and often debugged.<\/p>\n

Cramming these protocols onto a single SoC significantly increases hardware complexity. The more protocols there are communicating internally and externally on a chip, the more verification cycles are needed to validate the design.<\/p>\n

\"Figure<\/a>

Figure 2. The IoT increases demands on protocol usage per chip (Mentor Graphics)<\/p><\/div>\n

2. Larger designs<\/h4>\n

Greater protocol integration increases complexity and size. So do a widening array of functions, multiple processors, and embedded software. Consumers want products that can handle ever more content. These devices must offer integrated digital, audio, voice, and data that is always on and always connected.<\/p>\n

The higher the amount of integrated content, the more concurrency there will be. This results in harder to verify systems, ones that can contain billions of gates. The need for us to rethink verification is self-evident.<\/p>\n

\"Figure<\/a>

Figure 3. More integration, multi-functionality, multi-processors, and embedded software increase complexity (Mentor Graphics)<\/p><\/div>\n

3. Lower power consumption<\/h4>\n

Design decisions need to consider power, area, and performance. The IoT places particular emphasis on power. This obviously makes system-level power analysis and management key activities.<\/p>\n

Verification solutions that provide accurate power analysis early in the flow can help guarantee that you make design decisions that do lower consumption significantly. The accuracy of such an analysis depends upon measuring power in the context of the applications that will run on the final SoC. This is where\u00a0traditional testbench-based verification falls short. We need a better way of delivering analysis that matches the needs of IoT designers.<\/p>\n

\"Figure<\/a>

Figure 4. Digital simulation testbenches cannot capture accurate power measurements (Mentor Graphics)<\/p><\/div>\n

4. Greater software content<\/h4>\n

Traditional software verification running on a software simulator is losing steam. Simulation is too slow to fully stress test an SoC running billions of cycles or frames of data. If designers are entirely or even just heavily dependent on simulation, they have to compromise on functionality. They cannot fully understand what is really happening in their system or SoC because they cannot generate and isolate the corner cases that could cause a problem in the field.<\/p>\n

Also, more software content increases SoC development costs, given the rule of thumb that software requires between five and 10 software engineers for every hardware engineer. The time your software engineers spend on verification needs to be made as efficient as possible.<\/p>\n

Your coding team needs a verification solution that has the performance to boot the OS and run the software applications on the target hardware well before hardware prototypes are available. This solution must also have the capacity and speed to exercise the billions of cycles required to fully verify software.<\/p>\n

\"Figure<\/a>

Figure 5. Increasing SW content drives SoC development and costs (Mentor Graphics)<\/p><\/div>\n

5. Increasing network switch and router activity<\/h4>\n

The IoT is driving networking advances because consumers want more bandwidth, more multimedia, more video, and more audio streaming. Networking companies must therefore offer higher bandwidths, higher performance computing, and more content-focused applications. Ethernet and other networking standards are being extended and\/or introduced to address these needs with faster networking protocols and more ports to improve network service.<\/p>\n

For example, the enormous networking configurations required to meet demand compels developers of newer network chips to put thousands of Ethernet ports on a single SoC. It is already nearly impossible to provide connections for all of these ports in a hardware test environment. Therefore, networking companies need a way of exercising their designs in software.<\/p>\n

Emulation-led verification for IoT Networks<\/h3>\n

Today’s\u00a0hardware and software require an enormous amount of verification. And things are not getting any easier; rather they are getting more difficult. We need to remember that the need to create products within shortening deadlines is also intensifying. So how can emulation help you manage these pressures? Why is it becoming a \u2018must have\u2019 component of verification?<\/p>\n

The Mentor Graphics<\/a> emulation team determined that the best way to improve the verification of complex IoT and networking systems was to have its Veloce platform\u00a0replicate the way IoT companies approach design. That approach involves disconnecting the hardware and operating system (OS) from the applications that run on phones and other products. It makes sense because end-users care about the apps they want to use and want them to run on whatever OS or device they have.<\/p>\n

So, the Veloce emulation platform has been tailored to allow designers to test designs using Veloce applications in the same way. The verification applications (for example, coverage, SW debug, low power, etc.) are independent of the operating system (OS). Thus, the Veloce OS provides an interface to the emulator for Veloce verification applications or for applications developed either internally or by third parties. Because Veloce OS is compatible with any generation or model of the Veloce emulation hardware family, users benefit from seamless adoption from one platform to the next, preserving investments and supporting scalability as an owner\u2019s performance and capacity needs increase.<\/p>\n

\"Figure<\/a>

Figure 6. Veloce OS and emulation applications (Mentor Graphics)<\/p><\/div>\n

The Veloce OS also supports the Enterprise Server. It optimizes resource utilization and provides job queuing and prioritization using load-sharing management software. The Enterprise Server allows users to submit jobs from their desktops to Veloce emulation resources housed in datacenters anywhere in the world. It supports the concurrent use of Veloce emulation across multiple projects, teams, users, and use modes. It figures out where to most efficiently allocate a single or multiple projects to ensure the most efficient use of the Veloce resources. The result is highly efficient, worldwide, 24\/7 access to datacenter-friendly emulation capacity.<\/p>\n

But all of this would be for nothing were the peripherals and protocols required to exercise a design not themselves software-based. This is why Mentor developed VirtuaLAB<\/a>. It has already changed the way SoC-based emulation is performed, and has paved the way for the Enterprise Server capability, transforming the lab environment into a datacenter that requires only the emulator and workstations to execute the software versions of the protocol models. Since VirtuaLAB uses the same protocol IP and software stacks as the ICE hardware solutions, it delivers the same functionality as traditional ICE-based verification, giving users the accuracy of hardware, and the flexibility and repeatable results available with software.<\/p>\n

\"Figure<\/a>

Figure 7. VirtuaLAB Enterprise Server provides 24\/7 global access to multiple users and projects (Mentor Graphics)<\/p><\/div>\n

But then there are further benefits. Compared to ICE, these are substantial:<\/p>\n