\u201cThe number one thing we see for mixed-signal and custom design at 10nm is around multi-patterning and mask coloring. When the industry started work on 20nm, coloring during design was one of those nice-to-have things. But the foundries didn\u2019t want the designers to worry about coloring \u2013 that could all be handled on the manufacturing side,” explains Jeremiah Cessna, director of product management at Cadence.<\/p>\n
\u201cThe situation started to change at 16nm. All the people doing sensitive custom and analog design started saying \u2018I care which mask this is on\u2019,\u201d Cessna adds.<\/p>\n
An example is differential-pair circuits where the behavior of the matched pairs relative to each other is important. \u201cIf the two halves of the pair are split across two masks, I am amplifying the variability.\u201d<\/p>\n
At 10nm, changes to multi-patterning, which may include a shift to triple from double-patterning, will mean more of the design will need to be colored as part of the layout process. It will not be practical or desirable to perform mask coloring as a back-end manufacturing task.<\/p>\n
\u201cAnother thing we run into at 10nm is how you do the multi-patterning. You have the concept of \u2018good mask and \u2018bad mask.\u2019 People are asking which masks key signals go on so they can use the good metal where they care about the signal.\u201d<\/p>\n
As well as splitting the design between masks, custom designers will need to pay attention to how the individual masks are balanced so that one mask does not have a much higher local feature density than the others. The spacing rules are complicated by the need in analog design to use non-minimum width wires in order to improve conductivity or power handling ability.<\/p>\n
The solution used by early adopters has been to a technique based on width-based spacing patterns (WSPs). The spacing pattern approach is inspired by digital layout techniques where tracks are aligned to a preferred grid. In digital design, this supports a standard-cell structure where fat power and ground wires run between cells of a set height that contain a set number of possible parallel tracks for signal routing.<\/p>\n
Whereas a digital design will typically use a single cell library architecture across millions of gates, the custom or analog designer will generally have more choices, Cessna says: \u201cThe track patterns depend on the types of block you are doing. You pick the template you want for each one. The number of spacing templates in use varies from team to team. We have customers with five spacing patterns. Some, often who have been doing FinFET-based designs for some time, have hundreds. We see most people going in this direction.<\/p>\n
\u201cAlthough it is like the gridded place-and-route used in digital design, you can\u2019t use a digital router. It\u2019s analog constraints applied to a digitally inspired architecture,\u201d Cessna adds.<\/p>\n
A further consideration when looking at mask density and track sizing are parasitics such as electromigration and self-heating. A large array of FinFETs in a small area will cause local self-heating, causing not only changes in behavior but potential reliability issues. Similarly, the high current drive of the FinFET can lead to increased electromigration that will damage minimum-width wires if left unchecked.<\/p>\n
As a result, the electrically-aware flow introduced for the 20nm generation of processes continues to be an important element at 10nm. \u201cIf you run simulation on a circuit without layout information, that is a waste of simulation time,\u201d said Cessna, making early layout an important part of analog design at 10nm.<\/p>\n
Early layout is increasingly being supported by automation features in Virtuoso such as ModGens. \u201cA ModGen can be thought of as a a super P-cell of sorts. It can be used to provide you with a parameterized black box approach to manipulating layout where you can change the properties of the module without manually going in and editing the geometry by hand.<\/p>\n
\u201cThe first way we saw ModGens being used was in differential pairs. You don\u2019t physically implement differential pairs the same way at 16nm as you do at 28nm. Now, you need to care about density, the color balancing and other electrical issues. If they are laid out wrong, they will cause issues. But with the increased constraints on layout, there are only so many ways to do it correctly. This is where automation makes sense.\u201d<\/p>\n
The modules can use APIs to support the electrical analysis that then modifies their geometry once an initial post-layout simulation has been carried, ensuring that the layout is clean in terms of both design rules and reliability. \u201cThe current and other parameters extracted from the simulation feed into the ModGen. If anything is too small to support the design, it can be flagged as a violation,\u201d Cessna says.<\/p>\n
The use of automation and electrically-aware design in Virtuoso supports not just analog blocks, where density is not usually crucial, but custom digital where logic density is a key criterion, Cessna adds: \u201cIf you have a block that you are moving over from an older process and find that it has features that call for a change in the track template to support it and which could change the architecture of the cells, you want to know that as early as possible. This is where Virtuoso stands out.<\/p>\n
\u201cYou have real-time feedback on issues such as electromigration and design rules. Layout engineers spend a lot of time in interactive routing, trying to squeeze as much area as possible out of the design. So that real-time feedback is vital.<\/p>\n
\u201cIn addition, the ModGens provide an assisted-layout flow where the designer can fill out forms and the tool spits out correct-by-construction cells,\u201d Cessna adds.<\/p>\n
As design teams begin to think about the issues that 7nm will bring, Virtuoso has been designed to handle the likely changes, Cessna notes: \u201cFor 7nm there are requests for more than three-color support. So, Virtuoso can now support well more than three colors.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"
The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.<\/p>\n","protected":false},"author":327,"featured_media":8381,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[38],"tags":[1473,1395,1435,387,1614,1488],"coauthors":[993],"class_list":["post-8379","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ic-implementation","tag-10nm","tag-electrical-rule-checking","tag-electromigration","tag-mixed-signal-integration","tag-multi-patterning","tag-self-aligned-multiple-patterning","workflow-featured","organization-cadence-design-systems"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/8379","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/327"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=8379"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/8379\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media\/8381"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=8379"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=8379"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=8379"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=8379"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}