The combination of FPGAs and IP blocks enables teams to develop and try out complex designs quickly. Optimised approaches to managing and using third-party IP, and packaging your own IP for reuse, can help ensure that methodology issues don\u2019t undermine the advantages of using IP in FPGA-based designs.<\/p>\n
In the simplest IP creation process, a team develops an IP block, compresses the file and sends it to the design team, which unpacks it and integrates the RTL into the top level of its design, which is then synthesized and implemented as a whole.<\/p>\n
A slightly more complex approach sees the creation team including constraints with the RTL, which are then used to inform the place and route process.<\/p>\n
More complex distribution strategies are necessary if creators are distributing configurable IP, targeting specific implementation technologies, or for licensing reasons. An IP packaging tool is necessary so that end users can generate the specific version of the IP they need, target it to their choice of FPGA, and get a licensed file for integration. Tools such as Synopsys\u2019 Synplify can ingest all the IP files created by an IP vendor\u2019s generator tool and use them as input to its integration process.<\/p>\n
The flow you use to manage your IP will depend on a number of factors:<\/p>\n
IP is packaged in a number of ways, depending on three key parameters (see Figure 1):<\/p>\n
IP is delivered in three forms:<\/p>\n
Your IP integration strategy depends on a number of factors:<\/p>\n
There are various ways in which IP can be incorporated in a design: by being absorbed into the design\u2019s RTL, or incorporated as a white box, grey box or black box model.<\/p>\n
In an Absorb<\/em> methodology, the IP logic can be optimized as part of the larger design during synthesis. The netlist output by synthesis includes the IP logic, so there is no need to provide the IP separately to the place and route process.<\/p>\n In a white-box<\/em> methodology for gate-level IP, the IP netlist is added as a read-only model. Synthesis does not change the IP, whose netlist is used for timing and resource estimation. The netlist output by synthesis doesn\u2019t include the IP logic, which is added during place and route.<\/p>\n In a black-box<\/em> methodology for gate-level IP, a stub for the IP is included in the design RTL. Synthesis has no visibility of IP timing or resources, unless special attributes are added to the stub. The netlist output by synthesis doesn\u2019t include the IP logic, which is added during place-and-route.<\/p>\n Altera offers a \u2018grey-box<\/em>\u2019 flow, in which Altera tools generate a read-only netlist, which cannot be re-optimized, for the Synopsys Synplify tool. The IP netlist is used for timing and resource estimation. The netlist output by synthesis doesn\u2019t include the IP logic, which is added during place-and-route.<\/p>\n The difference between a grey-box and white-box netlist in this context is that a white-box netlist can also be used in Absorb mode.<\/p>\n The Xilinx Vivado IP Catalog tool generates Xilinx IP in two forms: plaintext RTL, and encrypted RTL. Plaintext IP can be absorbed during synthesis as part of the top-level design. Encrypted RTL is only readable by simulators. Vivado produces a gate-level netlist for Synplify to read.<\/p>\nNo URL for image<\/em>\n During the import process, Synplify automatically translates Vivado XDC constraints into Synplify FDC format constraints. The tool can import both RTL and netlist IP, and can handle single blocks or all the blocks in an IP directory at once.<\/p>\n Some best practices:<\/p>\n Synplify FGPA tools provide direct support for Altera IP. Megafunctions can be inferred and are modeled using \u2018clear-box\u2019 and grey-box models. Instances of LPMs (library of parameterized modules) can be merged into the design as a netlist.<\/p>\nNo URL for image<\/em>\n Some recommendations<\/p>\n Companies such as Synopsys, ARM and others also offer IP for use in FPGAs. Their IP blocks are shipped with Synplify project files, which can be added to a user design project as a sub-project. The RTL is accessible for synthesis, because it’s plaintext or has been delivered with embedded encryption keys that Synplify can unlock.<\/p>\n IP delivered in netlist format has already been synthesized in Synplify, which should mean better performance.<\/p>\n ASIC designs can be synthesized into an FPGA using Synplify, without having to replace any of the Synopsys DesignWare components. Synplify recognises DesignWare models that have been instantiated in the ASIC RTL and handles them automatically.<\/p>\n DesignWare Cores can also be used directly in FPGA designs. Synopsys has two tools, coreConsultant and coreAssembler, which can be used to configure DesignWare components and then generate the necessary RTL, constraints and scripts to be passed into Synplify as a project file, to be combined with the rest of your design.<\/p>\nNo URL for image<\/em>\n A typical IP package will contain a metadata file or a Synplify project file, RTL or netlist files, constraint files, and a configuration tool if the IP is configurable. The Synplify-import process adds a Synplify project file (PRJ), translated IP constraints (FDVC, and a constraints file for place and route if supplied.<\/p>\n Depending on how you expect the IP you are packaging to be used, you may want to encrypt it.<\/p>\n The IEEE is in the process of adopting the P1735 standard for encrypting IP, with support from Aldec, Altera, Cadence Design Systems, Mentor Graphics, Synopsys and Xilinx. The standard uses strong encryption to create \u2018digital envelopes\u2019 that enable multiple tools to read encrypted designs securely. It is up to the IP vendor to decide which EDA tools can read the IP.<\/p>\n The steps to created an IP block encrypted with P1735 are as follows:<\/p>\n Figure 6 shows how the encryption process works. Your unencrypted source is encrypted with a session key, creating an encrypted data block.<\/p>\n The session key is created using asymmetric encryption, using the software vendor\u2019s public key, to create the key block. The encrypted data block and key block are then bundled together to create a digital envelope. Each tool vendor gets a separate key block, based on their public key, and users can see which vendor\u2019s key block exists in the encrypted file.<\/p>\nNo URL for image<\/em>\n The decryption process in Synplify starts with the decryption envelope. The tool uses its own key block to decrypt the session key using a private key. The extracted session key is then used to decrypt the data block. This decryption process never writes the decrypted data on the disc. The design is synthesized and re-encrypted before it is written out in a file.<\/p>\nNo URL for image<\/em>\n Synplify includes an encryption script, and a public key.<\/p>\n Synplify supports a special design flow for the Xilinx Zynq-7000 all-programmable SoC.<\/p>\n It also supports the use of software IP models for prototype systems, for example to validate IP in a real-world environment. The solution is to use UMRbus and AMBA-based transactors to connect the virtual CPU subsystems to FPGA-based prototyping hardware.<\/p>\n Virtual prototyping<\/p>\n http:\/\/www.synopsys.com\/Systems\/VirtualPrototyping\/Pages\/default.aspx<\/a><\/p>\n Hybrid prototyping<\/p>\n http:\/\/www.synopsys.com\/Systems\/FPGABasedPrototyping\/Pages\/hybrid-prototyping.aspx<\/a><\/p>\n Synplify synthesis<\/p>\n http:\/\/www.synopsys.com\/Tools\/Implementation\/FPGAImplementation\/Pages\/default.aspx<\/a><\/p>\n Webinar: Getting the most out of IP-based FPGA design with Synplify – https:\/\/event.on24.com\/eventRegistration\/prereg\/register.jsp?eventid=907380&sessionid=1&key=5EA292D9A805767495ABEAFA515AB763&partnerref=web&cmp=WEBR-fpga100400-HPE<\/a><\/p>\n Parminder Gill is engineering project leader, FPGA implementation at Synopsys. He has 17 years of experience in FPGA implementation tools, RTL design, verification, and prototyping. Before joining Synopsys he was a senior manager at Synplicity,\u00a0leading SOC design team that created System Designer tool. He holds a BE in electronics from Thapar University, Patiala India.<\/p>\n <\/p>\n","protected":false},"excerpt":{"rendered":" How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices <\/p>\n","protected":false},"author":329,"featured_media":7738,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1386,160],"tags":[1814,1571,922,1684,1145,1812],"coauthors":[996],"class_list":["post-7723","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-assembly-integration","category-design-management","tag-altera","tag-ip-encryption","tag-ip-integration","tag-reuse","tag-vivado","tag-xilinx","workflow-technique","workflow-up-to-date","organization-synopsys"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/7723","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/329"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=7723"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/7723\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media\/7738"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=7723"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=7723"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=7723"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=7723"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}Using Xilinx Vivado IP<\/h2>\n
\n
Using Altera IP<\/h2>\n
\n
Working with third-party IP<\/h2>\n
Packaging and protecting IP for re-use<\/h2>\n
\n
Other Synplify features<\/h2>\n
Further information<\/b><\/h2>\n
Author<\/b><\/h2>\n
Company info<\/b><\/h2>\nSynopsys Corporate Headquarters<\/i><\/address>\n 690 East Middlefield Road<\/i><\/address>\nMountain View, CA 94043<\/i><\/address>\n(650) 584-5000<\/i><\/address>\n(800) 541-7737<\/i><\/address>\n\u00a0<\/i>www.synopsys.com<\/a><\/i><\/address>\n