{"id":7377,"date":"2014-08-27T18:07:37","date_gmt":"2014-08-27T18:07:37","guid":{"rendered":"https:\/\/www.techdesignforums.com\/practice\/?p=7377"},"modified":"2019-03-31T17:19:25","modified_gmt":"2019-03-31T17:19:25","slug":"criteria-migrate-finfet-process","status":"publish","type":"post","link":"https:\/\/www.techdesignforums.com\/practice\/technique\/criteria-migrate-finfet-process\/","title":{"rendered":"Six key criteria for deciding to migrate to a finFET process"},"content":{"rendered":"

Should your next SoC be built on a finFET<\/a> process, or should it stick with 28nm or 20nm<\/a> planar options? It\u2019s a question facing leading SoC developers as the foundry industry wrestles with the costs and complexity of this latest process transition.<\/p>\n

Things used to be simpler. Foundries would develop a denser process and designers who used it would \u2018automatically\u2019 gain improvements in the power consumption, performance and area of their designs – the so-called PPA benefits. Things aren\u2019t that simple for the shift to finFETs, so how do you decide whether to make the move?<\/p>\n

Before we answer that, let\u2019s recap what a finFET is and why it matters.<\/p>\n

Why finFETs matter<\/h2>\n

FinFETs are a response to the increasing power consumption of planar transistors, caused by leakage through the bulk silicon under the channel at advanced geometries. By moving the channel into a three-dimensional \u2018fin\u2019 above the surface of the bulk, the gate can take much stronger control of the channel, and leakage through the bulk is reduced. Lower dopant levels in the channel reduce variability, enabling lower threshold voltages and hence lower operating voltages, which ultimately reduces power consumption.<\/p>\n

There are downsides to the finFET. Because you can\u2019t vary the shape of the fin, the effective width of the transistor is quantized, which creates a new constraint for analog designers. Because And since the channel is isolated in the fin, you can\u2019t do body biasing<\/a> to reduce leakage, or boost performance at the cost of extra leakage. Parasitics<\/a> are higher, because of the dimensions of the device and its 3D shape. There are also new aging and self-heating mechanisms to be taken into account in circuit design.<\/p>\n

PPARCY – a framework for choosing a new process<\/h2>\n

FinFETs enable us to keep shrinking transistors without losing their performance advantages in a flood of leakage current. So why not make a PPA comparison between your current planar process and an emerging finFET process and make your decision on that basis?<\/p>\n

We\u2019re finding the decision-making process is not quite that simple. We believe that you need to make your choice using six criteria \u2013 power, performance, area, process readiness, cost, and yield \u2013 what we\u2019re calling the PPARCY framework. Let\u2019s take them one by one.<\/p>\n

Power<\/strong><\/h3>\n

FinFET processes have about half the leakage of the preceding planar processes, according to what we have seen in silicon from multiple foundries. Dynamic power has come down, and lower leakage enables lower threshold and operating voltages.<\/p>\n

Performance<\/strong><\/h3>\n

We think you\u2019ll see an average 30% speed increase going from a 28nm planar to a 16nm or 14nm finFET process.Using our ARC processor cores as a measure, when we compare our 12.5-track library at 28nm to our 16nm 9-track library, the 9-track finFET library offers greater performance. That\u2019s making people ask whether they\u2019ll even need a library with more tracks at 16nm.<\/p>\n

Area<\/strong><\/h3>\n

New process nodes usually bring a 50% area shrink, although the amount of improvement has been declining recently because of routing issues<\/a> in such dense processes. We\u2019re finding that for cells such as SRAMs, you can get about a 40% area reduction moving to a finFET process.<\/p>\n

Readiness<\/strong><\/h3>\n

There\u2019s not much point in worrying about moving to finFETs if the processes aren\u2019t ready.<\/p>\n

This is what has been publicly announced:<\/p>\n