{"id":6443,"date":"2014-01-28T10:00:08","date_gmt":"2014-01-28T10:00:08","guid":{"rendered":"https:\/\/www.techdesignforums.com\/practice\/?p=6443"},"modified":"2014-05-27T16:04:21","modified_gmt":"2014-05-27T16:04:21","slug":"advanced-design-emerging-process-nodes","status":"publish","type":"post","link":"https:\/\/www.techdesignforums.com\/practice\/technique\/advanced-design-emerging-process-nodes\/","title":{"rendered":"Are advanced designs only possible at emerging process nodes?"},"content":{"rendered":"

What does \u201cadvanced design\u201d mean in the context of today\u2019s chip industry? Until recently, advanced design was synonymous with making chips on emerging process nodes, but its meaning now includes the content of the design as well as the fabrication process. To be clear, the content of the design is made up of the chip\u2019s function, the algorithms coded into the hardware to achieve that function, and the architecture that defines the structure of the hardware.<\/span><\/p>\n

Today, advanced design is taking place at many technology nodes. Some advanced designs are noticeably present in our lives, such as the chips in our mobile phones and high-performance laptops, built on the latest technology nodes to achieve high-speed processing and extremely high levels of functional integration.<\/p>\n

Many other advanced designs are hiding in plain sight. They are in the cars we drive to work and the hearing aids people depend upon to keep up with conversations. These advanced designs are everywhere, because low power consumption is one of today\u2019s top design goals no matter what process the chips are made on. Achieving such very low power goals is only possible using the most advanced design methods. For example, there are automotive designs made on 180nm processes that use 12 voltage domains, a level of complexity that was undreamt of when that node was introduced in 1999.<\/p>\n

In the biomedical arena, hearing-aid designs go beyond voltage-domain power planning and apply advanced leakage-recovery and library-design techniques to extend the life of button cell batteries. And this is for aids that use new levels of digital signal processing to deliver increasingly effective hearing assistance and user comfort. This combination of advanced design techniques is being applied to multi-chip designs made on processes ranging from 130nm down to 65nm.<\/p>\n

The internet of things is also upon us. Home heating and cooling systems can already email us when an oil level is too low or a filter needs replacing. Soon our washing machine will negotiate with our dishwasher about the best use of hot water throughout the day. These devices don\u2019t need to operate at 2.5 GHz, and they won\u2019t need 100M plus gates. But they will use many of the same advanced design techniques used on chips being built on the latest, emerging technology nodes.<\/p>\n

So is advanced design the same as designing at the latest technology node? No. Advanced design is now as likely to be applied to chips that will be manufactured using established process nodes that have been around for decades, as well as the 20\/16\/10nm processes that are still emerging from labs to fabs.<\/p>\n

Company info<\/b><\/h2>\n
Synopsys Corporate Headquarters<\/i><\/address>\n
700 East Middlefield Road<\/i><\/address>\n
Mountain View, CA 94043<\/i><\/address>\n
(650) 584-5000<\/i><\/address>\n
(800) 541-7737<\/i><\/address>\n
\u00a0<\/i>www.synopsys.com<\/a><\/i><\/address>\n

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Advanced design isn\u2019t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.<\/p>\n","protected":false},"author":329,"featured_media":6475,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[38],"tags":[597,1478,975,1495,1497,1496,1414,1275],"coauthors":[996],"class_list":["post-6443","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ic-implementation","tag-130nm-and-below","tag-16nm-and-below","tag-65nm","tag-advanced-design","tag-emerging-nodes","tag-established-nodes","tag-internet-of-things","tag-power-architecture","workflow-expert-blog","workflow-incomplete","workflow-op-ed","workflow-up-to-date","organization-synopsys"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/6443","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/329"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=6443"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/6443\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media\/6475"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=6443"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=6443"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=6443"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=6443"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}