{"id":5738,"date":"2013-09-16T09:00:42","date_gmt":"2013-09-16T09:00:42","guid":{"rendered":"https:\/\/www.techdesignforums.com\/practice\/?p=5738"},"modified":"2019-03-31T17:30:54","modified_gmt":"2019-03-31T17:30:54","slug":"usb-3-0-link-layer","status":"publish","type":"post","link":"https:\/\/www.techdesignforums.com\/practice\/technique\/usb-3-0-link-layer\/","title":{"rendered":"The USB 3.0 Link Layer"},"content":{"rendered":"<p><a href=\"https:\/\/www.techdesignforums.com\/practicetechnique\/usb-3-0-protocol-layer-2\/\" target=\"_blank\" rel=\"noopener noreferrer\"><em>&lt;= Previous article: USB 3.0 Protocol Layers &#8211; part 2<\/em><\/a><\/p>\n<p>In the general SuperSpeed architecture, the Link Layer manages the port-to-port flow of data between the host and the device. A Link is the logical and physical connection between two ports (an upstream-facing port and a downstream-facing port).<\/p>\n<p>The Link Layer manages and controls the logical portion of the link, and is responsible for its reliability. Link commands are used for link-level data integrity, flow control, and link power management.<\/p>\n<div class=\"article_figure\"><a class=\"figure\" title=\"Figure 1 : The Link Layer manages and controls the logical part of a Link (Source: Synopsys)\" href=\"https:\/\/www.techdesignforums.com\/practicefiles\/2013\/09\/USB-University-diag-6-lrg.jpg\"><img decoding=\"async\" src=\"https:\/\/www.techdesignforums.com\/practicefiles\/2013\/09\/USB-University-diag-6-med.jpg\" alt=\"The Link Layer manages and controls the logical part of a Link (Source: Synopsys)\" \/><\/a><\/div><div class=\"article_figure\"><p class=\"figure_wrapper\"><span class=\"figure_title\">Figure 1 <\/span>The Link Layer manages and controls the logical part of a Link (Source: Synopsys)<\/p><\/div>\n<p>The functions of the Link Layer include:<\/p>\n<ul>\n<li>Link training, covering bit- and symbol-lock, and Rx equalization via TSEQ, TS1 and TS2 training order sets<\/li>\n<li>effective power management for four link power states<\/li>\n<li>handling low-frequency signaling for communications between two ports<\/li>\n<li>packet\/link commands formation, including packet framing with K-symbols<\/li>\n<li>error handling of various types<\/li>\n<\/ul>\n<p>The four low-power states of the Link layer are:<\/p>\n<ul>\n<li>U0, link active, the normal operational state<\/li>\n<li>U1, link idle &#8211; fast exit, in which the PLL remains on<\/li>\n<li>U2, link idle &#8211; slower exit, in which the PLL can be turned off<\/li>\n<li>U3, link suspend, in which the clock generation circuit can be turned off<\/li>\n<\/ul>\n<p>The Link Layer also handles Header Packet Framing, by taking the 12 bytes of each Header Packet created by the Protocol Layer and framing them with eight more bytes of information. These include 4 bytes to indicate the start of the Header Packet and the end of the Packet Framing, 2 bytes of cyclic redundancy check (CRC), and a 2 byte Link Control Word.<\/p>\n<p>Link Commands are used between two linked ports to communicate information between the upstream and the downstream port, ensuring link-level data integrity, flow control, and link power management. These commands are only sent from the transmitter link layer to receiver link layer, and are not routed onwards to other links.<\/p>\n<p>A Link Command Word handles packet acknowledgement and error recovery, packet flow control, and link power management. The Command Word includes fields with which a receiving port can indicate whether the header packet is good, bad or should be retried. Other fields provide information about requests to change power status, and a \u2018device present\u2019 indicator.<\/p>\n<p><em><a href=\"https:\/\/www.techdesignforums.com\/practicetechnique\/usb-3-0-physical-layer\/\" target=\"_blank\" rel=\"noopener noreferrer\">Next =&gt;\u00a0 USB 3.0 Physical Layer<\/a><\/em><\/p>\n<h2>Further information<\/h2>\n<p><em>If you are new to designing with USB, or looking for tips on implementing USB 3.0 IP, attend Synopsys&#8217; \u201cUSB 3.0 University.\u201d Topics in this instructional video series range from fuller descriptions of the USB 3.0 Link Layer protocol, USB 3.0 link states, and USB 3.0 Link commands. Click on the links below.<\/em><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-why-usb\" target=\"_blank\" rel=\"noopener noreferrer\">Why USB 3.0?<\/a><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-overview\" target=\"_blank\" rel=\"noopener noreferrer\">USB 3.0 Overview<\/a><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-functional-layer\" target=\"_blank\" rel=\"noopener noreferrer\">USB 3.0 Functional Layer<\/a><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-protocol-layer-1\" target=\"_blank\" rel=\"noopener noreferrer\">USB 3.0 Protocol Layer &#8211; Part 1<\/a><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-protocol-layer-2\" target=\"_blank\" rel=\"noopener noreferrer\">USB 3.0 Protocol Layer &#8211; Part 2<\/a><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-link-layer\" target=\"_blank\" rel=\"noopener noreferrer\">USB 3.0 Link Layer<\/a><\/p>\n<p><a href=\"http:\/\/www.synopsys.com\/cgi-bin\/dwusbuvs\/reg1.cgi?file=usb3-physical-layer\" target=\"_blank\" rel=\"noopener noreferrer\">USB 3.0 Physical Layer<\/a><\/p>\n<h2><\/h2>\n<h2><b>Company info<\/b><\/h2>\n<address><i>Synopsys Corporate Headquarters<\/i><\/address>\n<address><i>700 East Middlefield Road<\/i><\/address>\n<address><i>Mountain View, CA 94043<\/i><\/address>\n<address><i>(650) 584-5000<\/i><\/address>\n<address><i>(800) 541-7737<\/i><\/address>\n<address><i>\u00a0<\/i><i><a href=\"http:\/\/www.synopsys.com\">www.synopsys.com<\/a><\/i><\/address>\n","protected":false},"excerpt":{"rendered":"<p>A look at the way in which the USB 3.0 Link Layer manages the port-to-port flow of data between the host and the device.<\/p>\n","protected":false},"author":329,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1386],"tags":[557,555],"coauthors":[996],"class_list":["post-5738","post","type-post","status-publish","format-standard","hentry","category-assembly-integration","tag-superspeed","tag-usb-3-0","workflow-technique","workflow-up-to-date","organization-synopsys"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/5738","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/329"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=5738"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/5738\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=5738"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=5738"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=5738"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=5738"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}