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<\/a><\/div>Figure 1 <\/span>Attempts to solve double patterning issues can easily lead to loops<\/p><\/div>\n It is very easy to create a design-rule checking (DRC) \u201cloop,\u201d which is a coloring conflict that cannot converge on a solution that works. And in many cases, it will be necessary to trace back a number of steps to unravel how the loop was created.<\/p>\n Handling double patterning properly is a major concern for custom designers of standard cells, memories, and I\/Os. These designers must be cognizant of coloring as they create layouts to optimize area. It is difficult to achieve a high density while making the design decomposable. According to some reports, standard cells that previously took four hours to lay out sometimes take a week at 20nm, because designers have to keep re-running verification as they try to pack decomposable cells as tightly as possible.<\/p>\n Analog designers are concerned about the mismatches that an additional mask can cause. Double patterning impacts electrical performance because different masks on a given layer will shift during the manufacturing process. This mask shift causes variations that have a direct impact on RC and the interconnect. As a result, parasitic matching can become very challenging between elements that are rendered using different masks.<\/p>\n Figure 2 <\/span>Mask shifts can occur with double patterning<\/p><\/div>\n EDA tools can help automate the colorized decomposition process and can help ensure correctness. In a 20nm-aware toolset, all physical design tools should be double patterning\u2012aware, including placement, routing, extraction, and physical verification. For example, extraction must be able to predict the capacitance variation resulting from mask shift.<\/p>\n Another capability that\u2019s needed is automated color-aware layout. Here, color conflicts are avoided as the layout designer draws shapes and places cells. Once a shape is dropped into place, the tool automatically makes any needed coloring changes. Locking color choices down in the design phase sets a constraint for the manufacturer and helps to ensure that matching is correct by placing pairs of nets or devices on the same mask.<\/p>\n Instead of running signoff verification once every four hours, a quick double patterning check should be run after every editing command. In this way errors can be fixed quickly, and designers don\u2019t end up with DRC loops that may take many steps to unwind.<\/p>\n At 20nm, it\u2019s not enough to model the performance of a transistor or cell in isolation. The environment around a device will change its behavior, a phenomenon captured by the term LDE. Although LDE became apparent at 28nm, the problem has grown significantly worse at 20nm, where cells are much closer together. At 20nm, up to 30 per cent of device performance can be attributed to the layout \u2018context\u2019. For example, the voltage threshold of a transistor will change based on how close the device is to the edge of a well \u2013 this is called the well proximity effect.<\/p>\n Other modifiers of device performance include the distance between gates \u2013 including dummy poly \u2013 which has a direct effect on the drain current of the transistor. This is known as the poly spacing effect. Another major cause of LDE is mechanical stress, which is often intentionally induced to improve CMOS transistor performance. For example, a dual stress liner is a silicon nitride (SiN) capping layer that is intentionally deposited to be compressive on PMOS and tensile on NMOS. Such stresses improve the performance of either form of transistor. Nonetheless, it results in variability that may make it difficult to close timing. Stress is also unintentionally induced through technologies such as shallow trench isolation, which isolates transistors and determines active-to-active spacing.<\/p>\n LDE cannot be modeled in Pcells (parametized cells) or device models. As a result, it is no longer enough to create a schematic, pick a topology, run a simulation, and throw it over the wall to a layout designer. At 20nm, circuit designers have to consider layout context as well as device topology, and they need to simulate with layout effects prior to layout completion. This may sound paradoxical, but it is possible to identify devices that are sensitive to LDE and thus allow the designer to recognize which components need greater care in layout. Less sensitive devices can be placed closer to well boundaries, for example. Circuit designers can also make use of LDE simulation using partial layouts and LDE-aware layout module generators. Layout engineers can use LDE hotspot detection and fixing.<\/p>\n Figure 3 <\/span>The increase in layout-dependent effects with reductions in geometry<\/p><\/div>\n The underlying technology that is needed is context-driven placement and optimization that can determine how different cells are going to interact and how the layout context affects timing and power. The design tool should take care of LDE during both schematic and layout phases. But it\u2019s not just about tools. Circuit and layout designers have to learn to work together in new ways, with a much higher level of cooperation.<\/p>\n For many custom designers, 20nm is all about density. Local interconnect (LI) layers \u2013 also called middle-of-line (MOL) layers \u2013 offer a way to achieve very dense local routing below the first metal layer. There may be several of these layers available in a given process, and most don\u2019t use contacts. Instead, they connect by shape overlap without any need for a cut layer. Getting rid of contacts makes routing denser because contacts are bigger than nets, and can\u2019t be placed too close to nets.<\/p>\n Figure 4 <\/span>New types of local interconnect enable increased density at 20nm<\/p><\/div>\n However, designers need to be aware that LI layers have their own restrictive design rules. For example, LI shapes can only be rectangles, and they often have fixed directions with length constraints.<\/p>\n At 20nm, there may be more than 5,000 design rule checks. Some 1,000 new rules have been added since the 90nm process node, and double patterning alone requires 30 to 40 checks. The 20nm node adds another 400 new advanced rules such as wrong width and wrong spacing, discrete width and spacing, and special rules for pin access on cells. Custom and mixed-signal designers will face directional orientation rules, specific rules regarding length\/width and transistor proximity, and new rules governing legal inter-digitation patterns.<\/p>\n An important point to remember is that 20nm doesn\u2019t just bring in more rules; it brings in more complex rules. Simple rules of thumb or memorization won\u2019t work any more. What\u2019s needed is a design system that can check design rules as the design progresses, rather than waiting for a final signoff check.<\/p>\n Transistors at 20nm are very small and very fast, and variation is a constant challenge. Transistors are sensitive to channel length and channel doping, and transistor behavior is subject to short-channel effects. Custom designers must minimize leakage, ensure reliability, and achieve reasonable yields.<\/p>\n The reality is that 20nm transistors were designed for achieving high densities in digital design, not for optimizing leakage or gain in custom\/analog design. A limited set of device sizes are available for design. Width and length parameters are limited to a small set of values, and with fewer choices, manually tuning transistors to meet specs (such as gain) is difficult.<\/p>\n Below 20nm many, if not most, designs will use a new type of transistor called a FinFET. In a FinFET, the transistor gate wraps around three sides of the transistor\u2019s elevated channel, or \u2018fin\u2019. This forms conducting channels on three sides of the vertical fin structure, providing much more control over current than planar transistors. Multiple fins can be used to provide additional current. FinFETs promise greatly reduced power at a given level of performance.<\/p>\n However, FinFETs raise some challenges for custom\/analog designers. One constraint is that all the fins on the transistors on a given chip must be the same width and height. Designers can add fins to increase the width, but this can only be done in discrete increments\u2014you can add 2 fins or 3 fins, but not 2.75 fins. In contrast, planar transistors can be adjusted to any channel width in order to meet specifications.<\/p>\n Other challenges include additional design rules, manufacturing variations in the width and height of fins, and metal and via resistance. SPICE models with additional parameters will be needed for the FinFETs, and simulators must be able to interpret them. Extraction tools must be aware of the capacitance and resistance that arises from 3D transistor structures. Layout tools will have to be optimized to handle FinFETs. And like any new technology, FinFETS will require ecosystem support including EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes.<\/p>\n To resolve the challenges described in the above sections, every tool in the custom\/analog flow needs to be aware of the changes that 20nm brings, including double patterning, LDE, local interconnect, complex design rules, device variation, and FinFETs. But it is not enough to just improve tools. What is needed is a new methodology that provides a higher level of automation than existing flows. In this methodology, circuit and layout designers will exchange and share information, \u201dpartial layout\u201d will provide early estimates of parasitics and LDE, and an in-design signoff approach will greatly shorten final signoff runs.<\/p>\n The traditional custom\/analog flow is a manual, \u201cthrow it over the wall\u201d approach. Circuit designers do schematic entry and run an ideal simulation without layout parasitics. The design is tossed to layout designers who handle device creation, manual placement, and manual routing. Next comes physical verification, extraction, and a final simulation. It\u2019s a time-consuming, serial methodology in which issues are exposed very late in the design process, and many design iterations may occur. Without changing this approach, blocks that took four hours to lay out at 28nm could easily take a week at 20nm.<\/p>\n<\/a><\/div>2. Layout-Dependent Effects<\/h2>\n
<\/a><\/div>3. Interconnect layers<\/h2>\n
<\/a><\/div>4. Design rules<\/h2>\n
5. Device complexity and variation<\/h2>\n
A new methodology<\/h2>\n