![\"\"](\"https:\/\/www.techdesignforums.com\/practicefiles\/2012\/08\/tdf-ment-aug12-fig1-lrg.jpg\")
<\/a><\/div>\nFigure 1<\/span> The chain test results also help us understand the type of defect that haunts our scan chains. As shown in Figure 1 and for additional models in Table 1, different defect types will yield different chain test results. A single delay defect will, for instance, result in the correct sequence appearing at the output pins, but with a one-cycle offset.<\/p>\n Table 1<\/span> While detecting a scan chain defect is trivial, identifying the defect location is much more complex. Knowing the exact location of the defect is crucial for bring-up, failure analysis (FA), and debug applications. The chain test results will not give any indication of where in the chain the defect is located. Depending on the type of defect, it is also virtually impossible to determine how many defects exist on each failing chain.<\/p>\n Since we cannot identify the defect location from the chain test results, we have to take a more sophisticated approach. There are four general ways of identifying scan chain defects. These are:<\/p>\n This article focuses on software-based diagnosis, which is based on production test results and does not require any additional test time or dedicated hardware equipment. Software-based diagnosis is offered by all commercial automatic test pattern generation (ATPG) tool vendors, and is loosely based on ATPG technology.<\/p>\n A typical flow for scan-chain diagnosis is shown in Figure 2. An ATPG software tool is initially used to generate test patterns for a device. These patterns include chain patterns and the scan patterns that target faults in the functional circuitry of the design.<\/p>\n When these patterns are executed on the tester (ATE), failures have to be collected for both the chain patterns and the scan patterns. Typically, failures from at least 32 scan patterns are required to achieve good diagnosis results. The diagnosis software then uses the gate-level representation of the design, test patterns, and the tester fail data to identify the location and type of scan-chain defects.<\/p>\n Figure 2<\/span> A typical diagnosis tool will use a collection of algorithms to provide the best possible results, but to get a basic understanding, we will take a closer look at the simulation technique, shown in Figure 3.<\/p>\n Figure 3<\/span> In this example, there is a \u2018stuck-at\u2019 defect in one of the scan chains. When a scan pattern is shifted into the chains, all the cells on the input side of the defect (labeled B in Figure 3) are correctly loaded, but the defect corrupts the cells on the output side of the defect, so that these cells may have incorrect values. During the scan capture, the loaded values propagate through the functional circuitry and may be captured in other scan cells. Cells with fan-ins, including the incorrectly loaded scan cells (labeled C), may capture incorrect values, while cells with inputs fanning in from the correctly loaded scan cells (labeled D), capture the correct data. When data is shifted out of the chains, the cells on the input side of the chain defect (B) will be corrupted so that incorrect values may occur on the output pins, while the cells on the right side of the defect that are fed by data from good chains (E) will capture correct data.<\/p>\n By now you may have noticed the use of the word \u201cmay\u201d in the previous sentences. Whether or not incorrect data is captured as a result of the defect depends on whether the faulty behavior differs from the expected behavior. For instance, if the expected value for all the \u2018B\u2019 cells is 1, then no failures will be observed when the pattern is shifted out. By analyzing the failures from multiple failing scan patterns, and tracing failures back to the origin, diagnosis tools can use this simulation approach to identify the failing locations.<\/p>\n The simulation approach alone may be insufficient to provide accurate results, especially in cases of multiple and intermittent defects. For large designs, simulation runtimes can be very high due to the amount of fail data that has to be simulated. New techniques have therefore emerged to help address these concerns. Profiling [4] and dictionary-[5] based approaches can help improve accuracy, resolution, and runtime. Technology has also been developed to ensure that diagnosis is compatible with on-chip compression [6]. These new approaches make scan-chain diagnosis a viable solution for even the largest designs for both low-volume applications such as failure analysis, and volume diagnosis applications for yield analysis [7-8].<\/p>\n In a recent study, a semiconductor company suffered from lower than expected yields on certain wafers of several products on a relatively new 40nm process [9]. More than 50% of die with failures in the digital circuitry were caused by scan-chain defects. To increase the chance of successful physical failure analysis (PFA) results, fail data was collected from about 100 failing die. Of these, 61 devices had diagnosis results deemed good enough to be used as starting point for PFA. The requirements were set to a diagnosis score larger than 95, a diagnosed chain segment of less than three scan cells, and less than four faulty scan chains. Five devices with the best diagnosis results were selected for PFA, and defects correctly identified in all five cases, as indicated in<\/p>\n Figure 4<\/span> Of the five devices analyzed, poly residue was found in four. The last device had a defect at the closed-loop contact-etch stop layer (CESL).<\/p>\n Software-based scan-chain diagnosis is an effective and automatable tool for debugging broken scan chains as part of a device bring-up, failure analysis, and yield-analysis process. The technology has been proven by many industrial cases for a wide range of scenarios [10].<\/p>\n [1] Y. Huang, R. Guo, W.-T. Cheng, J. C.M. Li, \u201cSurvey of Scan Chain Diagnosis\u201d, IEEE Design and Test of Computers, May 2008, pp. 240-248. Geir Eide earned an MS in electrical and computer engineering from the University of California at Santa Barbara and is a product marketing manager in the Silicon Test Solutions group at Mentor Graphics Corporation. He can be contacted at geir_eide@mentor.com<\/a>.<\/p>\n
\nUsing a scan chain test to observe failing scan chains (Source: Mentor Graphics \u2013 click image to enlarge)<\/p>\n<\/div>\n<\/a><\/div>\n
\nChain fault models determined by chain patterns (shift-in: 001100110011) (Source: Mentor Graphics \u2013 click image to enlarge)<\/p>\n<\/div>\nLocation, location, location<\/h2>\n
\n
<\/a><\/div>\n
\nScan-chain diagnosis flow (Source: Mentor Graphics \u2013 click image to enlarge)<\/p>\n<\/div>\n<\/a><\/div>\n
\nSimulation of scan patterns to identify failing cell location (Source: Mentor Graphics \u2013 click image to enlarge)<\/p>\n<\/div>\nTaking scan-chain diagnosis to the next level<\/h2>\n
Case Study<\/h2>\n
<\/a><\/div>\n
\nPhysical failure analysis images from locations identified by scan chain diagnosis (Source: Mentor Graphics \u2013 click image to enlarge)<\/p>\n<\/div>\nConclusion<\/h2>\n
References<\/h2>\n
\n[2] A. Crouch, \u201cDebugging and Diagnosing Scan Chains\u201d, Electronic Device Failure Analysis, January 2005, pp. 16-24
\n[3] S. Kasapi, W. Lo, J. Liao, B. Cory, H. Marks, \u201cAdvanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing\u201d, Proc. of International Symposium of Testing and Failure Analysis (ISTFA) 2011, pp. 12-17. www.asminternational.org.
\n[4] Y. Huang, W.-T. Cheng, R. Guo, T.-P. Tai, F.-M. Kuo, Y.-S. Chen, \u201cScan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns\u201d, Asian Test Symoposium (ATS) 2009, pp. 35-40.
\n[5] R. Guo, Y. Huang, W.-T. Cheng, \u201cA complete test set to diagnose scan chain failures\u201d, Asian Test Symoposium (ATS) 2007, pp. 1-10.
\n[6] Y. Huang, W.-T. Cheng, J. Rajski, \u201cCompressed pattern diagnosis for scan chain failures\u201d, IEEE International Test Conference (ITC) 2005, pp. 744-751.
\n[7] C. Schuermyer, B. Benware, G. Rhodes, D. Appello, V. Tancorre, O. Riewer, \u201cDevice Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis\u201d, Proc. of International Symposium of Testing and Failure Analysis (ISTFA) 2011, pp. 91-97. www.asminternational.org
\n[8] F.-M. Kuo, Y.-S. Chen, \u201cYield Ramp up by Scan Chain Diagnosis\u201d, Asian Test Symposium (ATS) 2009, pp. 94-95.
\n[9] Y. Huang, B. Benware, W.-T. Cheng, T.-P. Tai, F.-M. Kuo, Y.-S. Chen, \u201cCase Study of Scan Chain Diagnosis and PFA on a Low Yield Wafer\u201d, IEEE International Test Conference (ITC) 2010, poster.
\n[10] Y. Huang, \u201cYield Improvement by Scan Chain Defects Diagnosis\u201d, ASM International webinar, http:\/\/www.mentor.com\/products\/silicon-yield\/multimedia<\/p>\nAbout the Authors<\/h2>\n