{"id":2796,"date":"2012-04-25T09:30:10","date_gmt":"2012-04-25T09:30:10","guid":{"rendered":"https:\/\/www.techdesignforums.com\/eda\/?p=2796"},"modified":"2014-06-28T12:38:36","modified_gmt":"2014-06-28T12:38:36","slug":"emulation-delivers-energy-efficiencies-and-economies-of-scale","status":"publish","type":"post","link":"https:\/\/www.techdesignforums.com\/practice\/technique\/emulation-delivers-energy-efficiencies-and-economies-of-scale\/","title":{"rendered":"Emulation delivers energy efficiencies and economies of scale"},"content":{"rendered":"

When we talk about green technologies, we\u2019re really talking about more sustainable ways of doing business. This approach goes beyond the convenience of charging your batteries less often. Sustainability implies doing more with less. Best business practices dictate that we do it better.<\/p>\n

Fortuitously, keeping a company in the black and doing it in a green way are not exclusive concepts; they are inextricably intertwined. Several European countries have already decided that a green economy is the only profitable economy. It makes sense that using resources more effectively reduces waste and yields a positive return for business.<\/p>\n

This is why the development of more efficient technologies is playing a starring role in healthy, sustainable economies and profitable companies. It\u2019s also why we\u2019re seeing the emergence of a new class of emulators (also known as hardware-assisted verification accelerators) that have been developed to verify larger, system-level designs in a more sustainable way.<\/p>\n

Emulation savings<\/strong><\/h2>\n

An emulator is a special-purpose computer designed to handle the functional verification of complex integrated circuits and system-on-chip (SoC) designs. The motivation for creating these single-function computers is to deliver a higher-capacity, more efficient system that occupies less space and consumes less power than the general-purpose computers used for simulation.<\/p>\n

Emulators save time. They implement a design in physical hardware, so they can verify it orders of magnitude more quickly than the complex software models used in digital simulation.<\/p>\n

Emulators save space. The complexity of multimillion-gate SoC designs means that it takes hundreds, even thousands of computers to simulate them as software models. Emulators can compile and run 500 million gate SoC designs in a single three-by-four foot chassis.<\/p>\n

And emulators save energy, handling in dedicated hardware what it would take a warehouse full of general-purpose computers to run as software. The upshot is that hardware emulators consume less power per verified gate, lowering the energy required for system-level verification. And emulation is getting greener. The latest emulators use up to 75 per cent less energy per verified gate.<\/p>\n

Mentor Graphics\u2019 latest emulator, Veloce2, is four times more power efficient than its previous generation. This has been enabled by using a new custom IC that doubles the capacity and speed of the emulator using the same number of emulation boards and the same-sized chassis. Thus it takes four of the older machines to emulate a design in the same amount of time as one of the newer machines. This means a fourfold reduction in energy consumption is possible by moving to the latest generation of emulator.<\/p>\n

\"\"<\/a><\/div>\n
\n

Figure 1<\/span>
\nA single Veloce 2 emulator has the capacity of a warehouse full of simulation computers. (Source: Mentor Graphics \u2013 click image to enlarge)<\/p>\n<\/div>\n

Not surprisingly, the difference between the number of simulation computers and the number of emulators required to verify multimillion gate SoCs has grown significantly, with implications for power consumption.<\/p>\n

This is because in emulation, designs typically run at about 1 MHz, whereas the typical simulation speed for a large design is around 100 Hz, making emulation about 10,000 times faster. For example, you would need 10,000 simulation computers to verify a 100-million gate design as quickly as a single emulator, if you could even partition the work across that many computers. In reality, you usually can\u2019t, so the simulation would have to be partitioned across fewer machines and then run for much longer and at a greater energy cost. The alternative, as often happens, is that the design team decides not to verify the entire SoC, taking the risk of a costly post-silicon failure.<\/p>\n

Running the numbers<\/strong><\/h2>\n

How real is the energy advantage of using emulators rather than simulators? Let\u2019s compare and contrast. One early adopter of Mentor\u2019s Veloce2 emulated a 60 million gate design in an hour, at an energy cost of 4 KWh. In comparison, the Dell t610 computer, widely used for simulation, draws 870 W (according to Dell). If it takes one simulator 10,000 hours to do the work of one hour of emulation, the equivalent energy cost would be: 870 watts x 10,000 hours.<\/em> If the customer chose to run their verification on one hundred computers, simulation would take just over four days, at an energy cost of 8,700 KWh. By rounding, then, emulation is 2,000 times more energy-efficient than simulation.<\/p>\n

In terms of space, while an emulator may take up a few square feet of floor space, companies would need much bigger facilities to house the 10,000 computers needed to deliver the same verification rate. These massive workstation farms take up a lot of space and incur significant construction, property, cooling, and climate-control costs. Even a more manageable (but slower) 100-machine simulation farm will need a dedicated room with custom cooling arrangements.<\/p>\n

It\u2019s difficult to put numbers on these costs, but when companies consider how much work emulators do and calculate the value of the energy savings they offer, the argument in favor of emulation is compelling.<\/p>\n

About the author<\/h2>\n

Jim Kenney has more than 25 years of experience in hardware emulation and logic simulation and has spent the bulk of his career at Teradyne and Mentor Graphics Corporation. At Mentor Graphics, Jim has held responsibility for analog, digital, and mixed-signal simulation, hardware\/software co-verification and hardware emulation. He is currently the marketing director for Mentor\u2019s Emulation Division. Jim holds a BSEE from Clemson University.<\/p>\n

About the company<\/h2>\n

<\/h3>\n

Mentor Graphics
\nWorldwide Headquarters
\n8005 SW Boeckman Rd
\nWilsonville
\nOR 97070-7777
\nUSA<\/p>\n

T: +1 503-685-7000
\nW:\u00a0www.mentor.com<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Can emulation save energy and space, as well as time, during the verification process? Some argue so.<\/p>\n","protected":false},"author":329,"featured_media":2833,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[35],"tags":[1047,1504,869,1056,995],"coauthors":[996],"class_list":["post-2796","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-design-verification","tag-emulation","tag-hardware-assisted-verification","tag-rtl-simulation","tag-sustainability","tag-virtual-prototypes"],"_links":{"self":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/2796","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/users\/329"}],"replies":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/comments?post=2796"}],"version-history":[{"count":0,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/posts\/2796\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media\/2833"}],"wp:attachment":[{"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/media?parent=2796"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/categories?post=2796"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/tags?post=2796"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.techdesignforums.com\/practice\/wp-json\/wp\/v2\/coauthors?post=2796"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}