Volume 5

December 1, 2008

Reality bites

This quarter’s issue leans slightly more toward coverage of incoming technologies than usual. Given the state of the economy around us, it can hardly hurt to look to a better future. At the same time, wise men in these new fields do seem quite keen on bringing us all down to earth. Consider: Professor Andre […]

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December 1, 2008

Designing an interactive GUI

Consumers want high-end GUIs on portable devices, but most MCUs—even those at 32bit—do not have the capacity to support embedded versions of these on their own. The article outlines the collaboration between Atmel, which has a family of customizable MCUs, and Amulet Technologies, a specialist in GUIs based on a compressed version of HTML. It […]

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December 1, 2008

Tightening the loop on coverage closure

The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so […]

December 1, 2008

Streamlining software development for a hardware ecosystem

Software accounts for more than half the development cost for a complex system-on-chip (SoC) platform at the 45nm process node or below. The availability of fundamental software such as compilers, debuggers, operating systems and industry-specific middleware determines the success or failure of a chip design. In simple terms, if there is little or no software […]

December 1, 2008

Combining yield and performance in behavioral models for analog ICs

The article describes an algorithm that combines performance and variation objectives in a behavioral model for a given analog circuit topology and process. The tradeoffs between performance and yield are analyzed using a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a signi?cant improvement in overall simulation time and ef? ciency compared to […]

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December 1, 2008

OCP performance monitoring with programmable instruments

The process of proving the system is working and performing optimally, under all application and environmental conditions, has become too inefficient and difficult for existing methodologies. Traditional methods for addressing post-silicon requirements have reached the point of diminishing returns. What was once an exercise of designing, implementing and verifying 25,000 to 50,000 gates of instrumentation […]

December 1, 2008

No silicon leapfrog

Andre Geim When you were young, did you enjoy bouncing around on a trampoline? If so, try this for size. Imagine a membrane about 275 miles long, one mile deep and an average of 10 miles wide. These dimensions matter. Because this sheet of material covers the entire Grand Canyon—and before you go bouncing on […]

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December 1, 2008

No double-quick growth for DDR3

Lane Mason Marc Greenberg DDR3 DRAMs still languish around the edges of the market despite their supposed attraction in terms of power and performance, the widespread availability of product, and the presence of a supposedly ‘evolved’ ecosystem and implementation infrastructure. Just over 18 months ago, Intel launched a major Go To DDR3 market initiative at […]

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December 1, 2008

License to profit

Guy Haas Managing EDA software involves more than monitoring and studying usage across various tools and features. An effective approach will help the enterprise reduce engineering software costs, reach better and more informed business decisions, become more responsive and ensure compliance with software licenses. To understand how to develop such strategies, we need to look […]

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December 1, 2008

IP hardens up again

Richard Goering System-on-chip designers who work with third-party silicon intellectual property (IP) will see some significant changes at 32nm and below. Physical IP will be highly optimized to specific processes, following intense collaborations between large IP providers and foundries. Processor IP may become less synthesizable and make more use of hard macros. On the plus […]

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