September 2007

November 1, 2007

What to look for when using an external PCB design center

The successful completion of complex PCB layouts requires a combination of highly skilled and experienced layout designers, a structured front-to-back design process, and advanced EDA toolsets. Success can be defined as meeting or exceeding all electrical, mechanical, and manufacturing requirements, and, where an external PCB design center is involved, satisfying the client in all interactions [...]
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September 1, 2007

What to look for when using an external PCB design center

The paper outlines the criteria upon which an OEM should make its selection of a third-party PCB design supplier. It groups these into three main categories. Staff with appropriate technical and communications skills. Comprehensive and fully documented design processes (ranging from the use of consistent design strategies to approaches to component library maintenance). Tool support […]

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September 1, 2007

Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below

Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]

September 1, 2007

The hidden cost of EDA

There must be a better way to keep track of electronic engineering software licenses. EDA tools are very expensive, essential to R&D work, and must be properly maintained to ensure that commercial designs are completed on-schedule. Nevertheless, companies traditionally set aside little management time to put formal control systems in place for these assets. Consider […]

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September 1, 2007

Start Here

It is interesting to see how the once widespread concern over design-for-manufacturability (DFM) has begun to recede. Yes, progressive process nodes will present further fabrication challenges. However, users now believe that the EDA world is well-placed to address them. EDA vendors have added more depth and breadth to their offerings. Foundries have provided necessary data […]

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September 1, 2007

MPSoC and ‘The Vision Thing’

We have entered the era of the multi-processor system-on-chip (MPSoC) but it remains a major frustration that, for a technology that is so imminent and so necessary, there is as yet no real vision out there that goes beyond the parochial. Yes, ‘point’ issues are also being addressed, but we need to define the concept, […]

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September 1, 2007

Introducing new verification methods into a design flow: an industrial user’s view

Verification has become one of the main bottlenecks in hardware and system design. Several verification languages, methods and tools addressing different issues in the process have been developed by EDA vendors in recent years. This paper takes the industrial user’s point of view to explore the difficulties posed when introducing new verification methods into ‘naturally […]

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September 1, 2007

From algorithm to first 3.5G call in record time

Increasing system complexity is forcing design teams to avoid errors during the process of system refinement and reduce ambiguities during system implementation to a minimum. On the other hand, the system design approach they choose must enable a project to advance rapidly through all stages of refinement from an algorithmic model to a real system-on-chip […]

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September 1, 2007

Designing for the real world

Lew Counts It is not unusual for analog circuit designers to exhibit a wistful air of ‘been there, done that’, even if you would never catch them wearing the t-shirt. That goes double for Lewis Counts, vice president of analog technology at Analog Devices and a fellow with the sector giant. “There are things they’re […]

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September 1, 2007

Characterizing process variation in nanometer CMOS

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. This paper presents an overview of test structures for characterizing statistical variation of process parameters. It discusses the test structure design and characterization strategy for calibrating random […]

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