December 2005

July 5, 2012

Improving ASIC prototyping on multiple FPGAs through better partitioning

Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
December 1, 2005

Behavioral IP reuse methodology

No one disputes the promise inherent in the concept of design reuse. But the true value of what has been delivered so far is often debated. This paper proposes a reuse methodology that is both practical and real and which uses behavioral synthesis as its driving technology. It discusses the most basic elements of behavioral […]

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December 1, 2005

Applying some perspective to DFM

So far, the debate over design for manufacturing (DFM) has featured contributions from, principally, four groups: designers, manufacturers, EDA vendors and the consultancy community. It is becoming increasingly apparent that some other voices need to be heard and their positions integrated within any successful semiconductor DFM chain. One such group is fab equipment suppliers. The […]

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December 1, 2005

IP protection under OASIS

Companies and mask shops already have plans and policies to secure the storage and transmission of sensitive layout VLSI data. These include confidentiality and non-disclosure agreements, and encryption. However, traditional VLSI file formats such as GDSII never popularized the type of constructs that facilitate intellectual property (IP) protection. The OASIS format does have these constructs. […]

December 1, 2005

Meeting yield enhancement challenges

Nanometer scaling severely inhibits the path to achieve sustainable yield. In response more responsibility for forecasting potential failures must shift to design for manufacturing (DFM) methodologies that can be applied early in the design process. Yet, while these hold much promise, manufacturing test and failure analysis remains at the forefront of determining why chips fail. […]

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December 1, 2005

Analog verification IP and the next stage in the evolution of system-on-chip

Introduction Considerable effort is being exerted to improve the quality and success of system-on-chip (SoC) designs. Given the demand for more and more features, lower power requirements, and need for blazing speeds to handle increasing data for video and other hungry applications, it is no surprise that complex SoCs are becoming harder to verify. A […]

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December 1, 2005

Effects of InfiniBand fixture crosstalk on a synthesized eye diagram

Introduction A synthesized eye diagram begins with an accurate TDT measurement of a linear device. The validity of this approach has been proven across a number of case studies and is now commonly accepted in the communication industry. The measurement allows the device’s eye response to be accurately generated by an advanced synthesis algorithm such […]

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December 1, 2005

Start here

We end the year with an issue of EDA Tech Forum that places perhaps more emphasis on design for manufacture than any before it, with opinions from Gartner Dataquest, Mentor Graphics and Applied Materials. These give readers a chance to view this often controversial and misunderstood area from three different but important perspectives: those of […]

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December 1, 2005

Taking a broad view

The IEEE Council for EDA has opened its website at www.c-eda.org. Earlier this fall, the IEEE Council for Electronic Design Automation (CEDA) took on formal existence with the election of its first officers. Design consultant and one time DAC general chair Alfred Dunlop is its launch president. He sets out why this is a great […]

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December 1, 2005

Which ADC architecture is right for your application – Part One

Introduction Selecting the proper ADC can appear a formidable task, considering the thousands on the market. A direct approach is to go to the selection guides and parametric search engines. Enter the sampling rate, resolution, power supply voltage, and other properties. Click ‘find’. And hope for the best. But it’s usually not enough. How does […]

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