High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
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