This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.
What hardware designers can learn from software verification techniques such as agile, behaviour-driven development, code coverage and zero known defect strategies
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
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A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.
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