Architecture & Design

Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

High-performance vision-processing algorithms need optimized CNN engines to deliver the right performance within the power budget of embedded applications.

Using specialised processors to implement key AI computation tasks such as CNNs.

Building secure SoCs takes a methodical approach, careful study of possible attacks, and embedded hardware that can provide a Root of Trust

Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.

The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.

Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.

CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.

Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.

Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.