VHDL

May 29, 2014

Lint

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Guide  |  Topics: EDA - Verification  |  Tags: , , , , , ,
May 23, 2012

VHDL

VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
Guide  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,

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