Using VIP for cache coherency hardware implementations
Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
verification
Accelerated VIP solves firmware and driver integration and validation tradeoffs
Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.
Verification IP: the questions you should ask
How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Synthesizing assertions into hardware for faster silicon debug
Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
Where there’s a will… there’s a way to better VHDL verification
An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.
Efficient RC power grid verification using node elimination
To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
Left shifting DFM analysis into the PCB design flow
What do we mean by a ‘left shift’ in design for manufacturing (DFM) analysis? Think of it as moving the DFM analysis from a tool run by the manufacturer into an integrated solution within the printed circuit board (PCB) design system. It is a major advance in the design of PCBs, allowing users to ultimately [...]
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