
static timing analysis


Hierarchical signoff of SoC designs at advanced process nodes

Timing analysis shifts to statistical

Cadence’s path to digital implementation on 10nm

Lessons learned in the finFET trenches

It’s time to embrace objective-driven verification

Better management of timing closure and optimization
20nm timing analysis – a practical and scalable approach
Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below
Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]
Confronting chip assembly challenges
Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]
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