static checks

May 3, 2021

How automated static checks help verify complex circuits for better performance and reliability

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.

Article | Topics: EDA - Verification | Tags: electrostatic discharge, ESD, layout dependent effect (LDE), low-power design, low-power verification, power intent, static checks, static verification | Organizations: Siemens EDA

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