Tech Design Forums
Technique
process variation
process variation
All
(1)
Articles
(1)
December 2, 2016
Hierarchical signoff of SoC designs at advanced process nodes
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
Article | Topics:
IP - Assembly & Integration
,
EDA - IC Implementation
| Tags:
CMP
,
crosstalk
,
parasitic extraction
,
process variation
,
signoff
,
static timing analysis
| Organizations:
Synopsys
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
Tech Design Forum
EDA
EDA TOPICS
DFM
DFT
ESL
IC Implementation
Verification
MORE EDA
Expert Insights
Guides
EDA Home Page
IP
IP TOPICS
Assembly & Integration
Design Management
Selection
MORE IP
Expert Insights
Guides
IP Home Page
PCB
PCB TOPICS
Design Integrity
Layout & Routing
System Codesign
MORE PCB
Expert Insights
Guides
PCB Home Page
Embedded
EMBEDDED TOPICS
Architecture & Design
Integration & Debug
Platforms
User Experience
MORE EMBEDDED
Expert Insights
Guides
Embedded Home Page