power integrity

A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.

PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.

Seven core considerations will help you realize your PCB for the Internet of Things more effectively.

Reliability is growing to match security as a key challenge for PCB design. These tools and techniques will help you rise to it.

The introduction of the DDR4 memory-bus standard will allow system designers to meet aggressive performance targets for their next-generation systems. But the changes required to support the higher datarates of DDR4 place stringent demands on the PCB designer.

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.

Advanced PCB and IC technologies have to be matched with advanced design and analysis tools if companies are going to produce board designs that are right first time, on time.

Signal integrity (SI) issues have been around for a while, the result of ever-faster edge rates. Both SI and PI problems manifest themselves as data errors. Indeed, PI problems are often misdiagnosed as SI problems. As such, an understanding of power delivery issues is essential to the success of any board project, as is a [...]

Knowing where your application is consuming resources is a crucial step in minimizing energy usage. The article describes a toolset developed by high-profile ARM-based microcontroller (MCU) start-up Energy Micro that helps to achieve this overarching goal within the context of a parallel move to 32bit MCU resolution.