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physical verification
physical verification
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October 9, 2012
Physical verification of 20nm designs through integrated double-patterning analysis and repair
Finding and fixing double patterning problems in 20nm designs
Article | Topics:
EDA - DFM
,
IC Implementation
| Tags:
20nm
,
double patterning
,
physical verification
| Organizations:
Synopsys
September 12, 2012
Critical tools for 20nm design
A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
Article | Topics:
EDA - DFM
,
IC Implementation
| Tags:
20nm
,
DFM
,
double patterning
,
litho-friendly design
,
lithography
,
parasitic extraction
,
physical verification
,
place and route
| Organizations:
Synopsys
«
1
2
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