lithography

May 26, 2014
Unidirectionally routed M1 using SADP (Source: CMU/IBM)

Triple patterning and self-aligned double patterning (SADP)

In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
January 20, 2014
Jean-Marie Brunet is the Product Marketing Director for DFM at Mentor Graphics

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
January 13, 2014
Steffen Schulze is director of marketing for Calibre Mask Data Preparation at Mentor Graphics

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
September 6, 2012
Antun Domic

Getting ready for 20nm

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations:
January 16, 2012

Double patterning for sub-28nm ICs

Double patterning provides an alternative to using EUV lithography – making it possible to implement ICs on sub-28nm processes.
Guide  |  Topics: EDA - DFM  |  Tags: , , ,
August 23, 2011

Quantifying returns on litho-friendly design

By the time a serious lithography-related problem is identified at the fab, it is too late in the design process to make simple layout changes. To avoid or reduce design delays, Infineon Technologies uses lithography simulation to detect weak points in a layout and analyze the effect of lithography on the design’s electrical performance. Its [...]
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December 14, 2010

Bringing fabless players into manufacturing research

Sematech, the leading research consortium for semiconductor manufacturing, has launched a campaign to recruit members from the fabless sector. The move reflects the importance of making manufacturing decisions earlier in the design flow, and is also intended to get input from designers on implementations of such technologies as 3D interconnects, next-generation lithography and novel materials/structures.
Article  |  Topics: EDA - DFM  |  Tags: , ,
May 1, 2010

Using advanced planarity analysis to drive smarter filling strategies

Designers have been using dummy fill to address design for manufacturing for some time, but the process of simply wallpapering shapes into a design's "white space" to help it maintain planarity can no longer cope with the complex challenges presented at today's advanced process nodes. Not only is planarity harder to maintain, but there are [...]
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