finFET

July 9, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

One BSIM to rule them all

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
June 10, 2014
High-speed I/O eye diagram - thumbnail

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
December 9, 2013
Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

FinFET parasitics come under control

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
December 3, 2013
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:
May 29, 2013
FinFET capacitances diagram

How to design with finFETs

How to design with finFETs, including the impact on standard cells, IP, SRAM; the effects of fin quantization; extraction and parasitics; AMS issues and more.
May 2, 2013
Intel finfFET SEM

Physical verification of finFET and FD-SOI devices

A look at some of the design and physical verification challenges of working with finFET and FD-SOI devices, including their impact on layout, DRC and LVS.
Article  |  Topics: EDA - Verification  |  Tags: , , ,
April 22, 2013
Layout segment showing problem of color splitting with double patterning

The five key challenges of sub-28nm custom and analog design

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.
December 4, 2012
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:
August 23, 2011

Parting of the ways

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,

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