August 7, 2014
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
July 15, 2014
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
July 13, 2014
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
July 9, 2014
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
June 22, 2014
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
June 10, 2014
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
May 29, 2014
By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
December 9, 2013
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
December 3, 2013
The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
May 29, 2013
How to design with finFETs, including the impact on standard cells, IP, SRAM; the effects of fin quantization; extraction and parasitics; AMS issues and more.