DRC

Plasma induced damage (PID) in gate oxide is a threat to MOSFET circuit yield and reliability. How can you effectively combat this issue?

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.

Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.

Using on-demand rule checks during place-and-route boosts efficiency and design quality.

Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.

For physical verification and beyond, each process node requires new thinking, new tools and greater performance.

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.

A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.