DFM

May 1, 2010

Manufacturability and yield toward 22nm

This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]
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May 1, 2010

Extending critical area analysis to address design for reliability

The time-dependent dielectric breakdown (TDDB) of inter-metal dielectrics on large-scale chips is becoming an increasingly important reliability issue across several semiconductor markets. This mechanism can cause early failures in use and is difficult to detect by traditional test, and hard to control by traditional reliability techniques.
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May 1, 2010

Using DFM for competitive advantage

The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
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May 1, 2010

Manufacturing a profit

DFM is essential to differentiating your products in the market, says Luigi Capodieci
May 1, 2010

DFM matures

Engineering managers need to get their priorities in order for incoming process nodes, says analyst Gary Smith
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May 1, 2010

Not the one that got away

The purpose of this special issue of EDA Tech Forum is to try and cut through some of the confusion and even frustration that surrounds DFM as a concept. We cannot promise “DFM for Dummies,” but we do hope to give you a sense of how you might manage the process.
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September 1, 2009

System level DFM at 22nm

The article provides an overview of one common theme in the papers presented at a special session of the 2009 Design Automation Conference, Dawn of the 22nm Design Era. As such, we would recommend that readers wishing to access still more detail on this topic (in particular, on device structures for 22nm and project management […]

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June 1, 2009

Computational scaling: implications for design

The article presents the context for the use of computation scaling (CS) to eke out more from existing lithography tools until next-generation techniques are finally introduced. It discusses the critical elements in the CS ecosystem developed by IBM and partners to overcome roadblocks to optical scaling that demand the use of non-traditional techniques for the […]

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May 1, 2009

Access all areas

Since 130nm, you have either had an innovative approach to low-power design, or you have not had a business. From that node onwards, low-power requirements began to match raw performance in driving the R&D agenda. Where the cutting edge was once defined by communications infrastructure and programmable logic, consumer electronics (CE) started to become ever […]

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June 1, 2008

Migration of the Cell Broadband Engine to 45nm SOI

The paper describes some of the main challenges in the latest process shrink for the Cell Broadband Engine, developed jointly by IBM, Sony and Toshiba. The authors show how the move from a 65nm to a 45nm SOI process was achieved by concentrating on four primary goals: automating the migration; setting a 30% power reduction […]

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