Doc Formal: The crisis of confidence facing verification
Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
Design Management
Where tools end and best practices begin
Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
FPGA-based prototyping 3: Which board do I need?
Part three of our series looks at the choices you face as you decide whether to build or buy a board.
FPGA-based prototyping 2: Understand the real cost
Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.
FPGA-based prototyping 1: What’s all this buzz about?
This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.
Using standardized design flows to cut time to tape-out – and speed design-flow evolution
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Debugging the debug challenge
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Verification challenges require surgical precision
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Concurrent design: one team, one virtual location
Speeding up electronics design by learning lessons in increasing parallelism from computer science.
Optimizing cloud computing for faster semiconductor design
How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
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