DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
clock distribution
Clock tree synthesis
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
Enabling FPGA prototyping of large ASIC and SoC designs
How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
PLATINUM SPONSORS
View All Sponsors