Tech Design Forums
Technique
chip-level
chip-level
All
(1)
Articles
(1)
January 25, 2019
A better way to manage error reporting at the chip and block levels
In a continuous-build design flow, at which level should your error markers be addressed?
Article | Topics:
EDA - IC Implementation
| Tags:
block-level
,
chip-level
,
DRC
,
error markers
,
error reporting
,
place and route
| Organizations:
Siemens EDA
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
PLATINUM SPONSORS
View All Sponsors
twitter
facebook
RSS
Tech Design Forum
Log In
Register
Sponsors
Briefing
EDA
EDA TOPICS
DFM
DFT
ESL
IC Implementation
Verification
MORE EDA
Expert Insights
Guides
EDA Home Page
IP
IP TOPICS
Assembly & Integration
Design Management
Selection
MORE IP
Expert Insights
Guides
IP Home Page
PCB
PCB TOPICS
Design Integrity
Layout & Routing
System Codesign
MORE PCB
Expert Insights
Guides
PCB Home Page
Embedded
EMBEDDED TOPICS
Architecture & Design
Integration & Debug
Platforms
User Experience
MORE EMBEDDED
Expert Insights
Guides
Embedded Home Page
Search