Calibre

June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
April 14, 2020
Power ground check featim

How automated power/ground short checks slash time during implementation

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , ,   |  Organizations:
February 14, 2020
P2P-Feb20-featuredimage

A better way to debug P2P results

P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.
October 9, 2019
Dina Medhat - Mentor

An easier way to make reliability rules and checks more consistent

Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
July 27, 2019

Optimize your database with duplicate data deletion

Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
Article  |  Topics: EDA - DFM  |  Tags: , , , , , , ,   |  Organizations:
June 11, 2019
Dennis Joseph is a technical marketing engineer supporting Calibre interfaces in the Design-to-Silicon division of Mentor, a Siemens business. His primary focus is the support and enhancement of the Calibre DESIGNrev layout viewer. Dennis received an M.S. in Electrical and Computer Engineering from the University of Florida.

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:
March 25, 2019
Voltage-aware DRC featured image

Use evolving DRC to automate high-voltage and multi-power domain verification

Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , ,   |  Organizations:
May 15, 2017
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

The Wally Rhines interview – Part Two: AI, automotive and security

This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
December 9, 2013
Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

FinFET parasitics come under control

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors