ARC

April 28, 2014

Overcoming the power/performance paradox in processor IP

The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors