Placement optimizations push power and clock on Cortex-M7 project
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
40nm
Catching layout-dependent effects on-the-fly
New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
First fabless, now labless
Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain
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