14nm/16nm

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?

The paper describes several innovative modifications to standard design flows that enable new device technologies to be rapidly assessed at the system level. Cell libraries from these rapid flows are employed by a design flow description language (PSYCHIC) for the exploration of highly speculative ‘what if’ scenarios. These rapid design flows are used to explore […]