October 8, 2015
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
August 5, 2015
System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
July 14, 2015
A look at the USB Type-C connector and the enhanced data rates and charging facilities it will enable
June 25, 2015
How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
June 22, 2015
Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
July 9, 2014
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
November 11, 2013
In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
November 27, 2012
The Linux Trace Tookit next generation provides open source tracer technology that helps surmount debug and optimization challenges
November 16, 2012
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
October 30, 2012
An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.