Standards

October 8, 2015
Amol Herlekar, Synopsys

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Expert Insight  |  Topics: IP - Design Management, EDA - Verification  |  Tags: , ,   |  Organizations: ,
August 5, 2015
Power switch

‘Even the software guys are starting to talk in milliwatts’

System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
July 14, 2015
John Blyler is an experienced physicist, engineer, journalist, author and professor, and editor of IoT Embedded Systems

USB Type-C: what it is and why it matters

A look at the USB Type-C connector and the enhanced data rates and charging facilities it will enable
Expert Insight  |  Topics: Embedded - Architecture & Design  |  Tags: , , , ,   |  Organizations:
June 25, 2015

Applying agile techniques to IC design

How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
June 22, 2015

Verifying MIPI interfaces in SoCs

Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
Article  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , , , , ,   |  Organizations: ,
July 9, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

One BSIM to rule them all

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
November 11, 2013
Brian Fuller is editor in chief at Cadence Design Systems.

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
November 27, 2012
LTTng logo

How LTTng enables complex multicore system development

The Linux Trace Tookit next generation provides open source tracer technology that helps surmount debug and optimization challenges
Article  |  Topics: Embedded - Integration & Debug  |  Tags: , , ,   |  Organizations: ,
November 16, 2012
Stephen Pateras

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,
October 30, 2012
Mixed-Signal Methodology Guide

Verifying low-power intent in mixed-signal design

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations: ,

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