EDA

If you're going to be working on any aspect of multicore embedded system design, a newly published book titled "Real World Multicore Embedded Systems" will be an excellent guide.

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows

How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.

The growing verification challenge, and how to address it by coordinating multiple debug strategies.

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.