New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
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