Verification

July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
June 3, 2014

Synopsys adds formal, CDC, low-power checks to Verification Compiler

Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
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June 2, 2014

Real Intent’s Pranav Ashar on converging design and verification

Verify early and simulate as little as possible - the idea is familiar but how do you get there?
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June 2, 2014

Mentor’s Wally Rhines on tools as a cultural issue

Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
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May 24, 2014

Real Intent updates lint tool, adds Matlab and Simulink support

More lint rules, better SystemVerilog support, links to MATLAB and Simulink
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May 21, 2014

Verification perspectives 2: formal for the masses and graph-based techniques

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
April 28, 2014

Synopsys speeds HAPS prototyping with ProtoCompiler

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
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April 16, 2014

Verification perspectives: the growth of emulation

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
April 10, 2014

Mentor builds simulation-emulation bridge to ‘Verification 3.0’

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
March 28, 2014

Software quality acquisition to bring Synopsys “new friends”

Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
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