Verification

January 21, 2024

Take a deeper dive into BCI-ROM

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.
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December 5, 2023

Zero ASIC open sources system simulation/emulation platform

Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
November 30, 2023

Benchmarking the maturity of AI in EDA

Solido discusses how it has leveraged AI for SPICE level efficiency and the benchmarks it has used.
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November 20, 2023

Creating the right simulation build flow

What are your options and what is one of the latest simulator features that helps streamline your build?
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November 20, 2023

ETRI builds flow for AI chiplets

South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
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October 24, 2023

Flow evolution for the 3DIC/chiplet age

Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
August 8, 2023

Catch up with the state-of-the-art in ‘shift left’

Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
July 14, 2023

Cadence mixes know-how and AI to bridge RTL gap

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
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July 10, 2023

Calibre ‘shifts left’ into place and route

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
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July 10, 2023

Siemens fuels custom IC flows with artificial intelligence

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

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