Verification

December 18, 2014

Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL

The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
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October 28, 2014

10Gbit/s USB 3.1 IP and verification support on the way

USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
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September 30, 2014

Real Intent’s Meridian CDC flexes hierarchical muscle, adds flexible debug

Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
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September 29, 2014

Verification platform offers unified compile, debug environments

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
September 3, 2014

DVCon Europe focuses on systems design and verification

Focus on systemic issues matches DVCon Europe event to European interests
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July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
June 3, 2014

Synopsys adds formal, CDC, low-power checks to Verification Compiler

Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
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June 2, 2014

Real Intent’s Pranav Ashar on converging design and verification

Verify early and simulate as little as possible - the idea is familiar but how do you get there?
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June 2, 2014

Mentor’s Wally Rhines on tools as a cultural issue

Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
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May 24, 2014

Real Intent updates lint tool, adds Matlab and Simulink support

More lint rules, better SystemVerilog support, links to MATLAB and Simulink
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