Verification

April 16, 2014

Verification perspectives: the growth of emulation

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
April 10, 2014

Mentor builds simulation-emulation bridge to ‘Verification 3.0’

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
March 28, 2014

Software quality acquisition to bring Synopsys “new friends”

Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
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March 26, 2014

Better Software, Faster!: free virtual prototyping book available now

Free book explains virtual prototyping and includes case studies about virtual prototyping from Altera, Bosch, GM, Hitachi, Lauterbach, Linaro, Microsoft, Renesas, Ricoh, Siemens, and TI.
March 26, 2014

Synopsys strengthens analog and mixed-signal verification with VCS AMS

VCS AMS updates AMS verification tool and methodology
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March 26, 2014

Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation

Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
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March 4, 2014

Synopsys targets 5X performance gain with integrated verification suite

New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
October 11, 2013

Verification Futures rolls out in Europe next month

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
September 19, 2013

Real Intent updates X verification tool

Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
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June 18, 2013

Real Intent highlights hierarchical clock domain crossing with Meridian 5.0

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
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