A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
But the bridge standard's European backers still need greater support from the big EDA vendors.
High powered alliance develops TLM standards to address growing automotive and IoT concerns.
Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
Spice regressions, library characterisation and yield analysis are all being promoted as suitable for running on the cloud
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
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