Focus on systemic issues matches DVCon Europe event to European interests
More than 20 new features and improvements are added to the static functional tool.
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
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