Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
Some conservative decisions were important parts of AMD's design strategy for the 28nm core that's just been specified in PlayStation 4
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.
Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
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