Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
Spice regressions, library characterisation and yield analysis are all being promoted as suitable for running on the cloud
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Conference addresses formal verification techniques at levels to suit beginners through to experts
Online and physical conference focuses on achieving compliance with safety standards such as ISO26262, DO254, and DO178
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
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