USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Focus on systemic issues matches DVCon Europe event to European interests
More than 20 new features and improvements are added to the static functional tool.
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
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