Verification

June 20, 2017

Formal focus for Synopsys blog

Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
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June 14, 2017

DAC 2017 preview: Oski Technology

Oski Technology will offer a range of daily presentations at its DAC 2017 and useful technical advice in the main conference program.
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June 8, 2017

DAC 2017 preview: OneSpin

Formal, AI and UVM form key parts of the OneSpin agenda for this year's Design Automation Conference.
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May 16, 2017

Cadence adapts Jasper tools for CDC and lint

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
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May 12, 2017

Toshiba case study describes advanced thermal simulation

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.
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May 3, 2017

Master the verification challenge of PCIe-based NVMe storage

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.
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May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
April 13, 2017

DVCon China looms as submission deadline for Europe approaches

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
March 6, 2017

Mentor’s Xpedition virtualizes simulation for ruggedized, safety-critical designs

Xpedition adds vibration and acceleration analysis to shorten physical PCB test times for ruggedized and safety-critical designs.
March 2, 2017

How formal concentrates ISO 26262 fault analysis

Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.

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