Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Focus on systemic issues matches DVCon Europe event to European interests
More than 20 new features and improvements are added to the static functional tool.
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
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