Verification

November 14, 2018

Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm

Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
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October 17, 2018

FPGA playing verification catch-up as bugs escape

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
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July 20, 2018

Why the time has come for cloud-based emulation

Mentor has untethered its Veloce platform online because it feels more designs need emulation and the cloud can now support it.
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June 22, 2018

Mentor strikes deal to buy Austemper

Deal to buy functional safety specialist builds out the automotive and Industry 4.0 offerings for Mentor and its parent Siemens.
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June 21, 2018

DAC 2018 preview: Real Intent

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
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June 21, 2018

DAC 2018 preview: Breker Verification Systems

The portable stimulus pioneer will demonstrate how the technology and standard have been leveraged for its new Trek5 release.
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June 20, 2018

DAC 2018 preview: Austemper Design Systems

Functional safety specialist will demonstrate extensions to its own suite and co-host demos highlighting its collaboration with OneSpin Solutions.
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June 19, 2018

Mentor targets DRC efficiencies for place-and-route with Calibre RealTime Digital

Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
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June 6, 2018

Synopsys speeds PrimeTime with AI

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design
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