Verification

January 20, 2016

Catching complex CDC bugs in large SoCs

A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
December 18, 2015

Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
November 12, 2015

DVCon Europe: UVM-SystemC backers ready first draft

But the bridge standard's European backers still need greater support from the big EDA vendors.
November 12, 2015

DVCon Europe: Getting TLM to cope with proliferating ECUs and serial protocols

High powered alliance develops TLM standards to address growing automotive and IoT concerns.
October 19, 2015

Mentor targets next-gen Ethernet with emulation

Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
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September 16, 2015

Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates

Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
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June 24, 2015

Mediatek extends big.LITTLE strategy with ‘tri-cluster’ smartphone CPU

Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
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June 8, 2015

Synopsys to acquire Atrenta

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
June 7, 2015

DAC 2015 forecast: Cloudy with a chance of Spice installs

Spice regressions, library characterisation and yield analysis are all being promoted as suitable for running on the cloud
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May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.

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