Tested Component to System

October 6, 2015

Samsung taps Mentor tools for higher yielding close-loop DFM

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
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December 18, 2014

Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL

The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
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November 4, 2014

From Darwin to Mao: how multi-patterning could move up the flow

Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
October 24, 2014

Synopsys combines cell-aware, slack-based test to find transient defects, adds eFlash support

Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
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June 2, 2014

Mentor’s Wally Rhines on tools as a cultural issue

Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
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May 13, 2014

Mentor targets 10X cut in reliability test for power electronics

New MicReD power tester identifies failure causes without the need for post-test lab analysis
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November 4, 2013

Amkor keeps question mark next to ‘full’ 3D-IC in 2016

Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
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April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
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June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
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