Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
We’ve just heard from the Small Form Factor Special Interest Group (SFF-SIG) that the RS-DIMM rugged embedded memory featured in the latest print edition of Tech Design Forum and online has been renamed XR-DIMM (eXtreme Rugged Dual In-Line Memory Module) with immediate effect. Paul Rosenfeld, SFF-SIG’s president, says the change is intended to “reflect the […]
Wearing another hat, I recently got back from NABshow, the huge broadcast engineering event in Las Vegas. As a self-confessed movie buff, I enjoy it more than CES. Smaller crowds, too. Only about 90,000.