May 21, 2015
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
December 18, 2014
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
July 22, 2014
More than 20 new features and improvements are added to the static functional tool.
June 2, 2014
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
April 28, 2014
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
April 10, 2014
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
June 18, 2013
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
June 17, 2013
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
May 14, 2013
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
March 19, 2013
Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.