Product

May 24, 2014

Real Intent updates lint tool, adds Matlab and Simulink support

More lint rules, better SystemVerilog support, links to MATLAB and Simulink
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March 26, 2014

Synopsys strengthens analog and mixed-signal verification with VCS AMS

VCS AMS updates AMS verification tool and methodology
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March 24, 2014

Synopsys begins IC Compiler II roll-out

New data model and optimisation strategy, plus revised analysis engines update Synopsys's IC Compiler place and route tool
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March 17, 2014

Mentor begins to take wraps off Xpedition PCB software overhaul

New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
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February 7, 2014

Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%

Uses improved logic optimisations and a new approach to meeting timing.
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February 6, 2014

Cadence to buy Forte and build out HLS offering

EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
December 16, 2013

Synopsys puts physical IP prototypes into developers’ hands

Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
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July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
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October 26, 2012

Mentor Graphics CEO Wally Rhines – Interview

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
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October 24, 2012

Tile-based integration of analog functions enables power controller family

Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
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