More than 20 new features and improvements are added to the static functional tool.
As heterogeneous multicore SoCs move into the mainstream, embedded developers face increasing integration and debug challenges.
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
VCS AMS updates AMS verification tool and methodology
New data model and optimisation strategy, plus revised analysis engines update Synopsys's IC Compiler place and route tool
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
Uses improved logic optimisations and a new approach to meeting timing.
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
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