Product

February 6, 2014

Cadence to buy Forte and build out HLS offering

EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
December 16, 2013

Synopsys puts physical IP prototypes into developers’ hands

Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
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July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
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October 26, 2012

Mentor Graphics CEO Wally Rhines – Interview

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
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October 24, 2012

Tile-based integration of analog functions enables power controller family

Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
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October 8, 2012

Synopsys buys EVE and the death of dogma

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.
July 26, 2012

Xilinx extends Vivado availability

Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.
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May 3, 2012

Technical Newsletter #4: Verification, Emulation, Prototyping

This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.
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March 26, 2012

Synopsys builds 3D into tool portfolio

At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
March 15, 2012

DATE notebook: Constraints smooth path for FPGA synthesis

Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.

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