More lint rules, better SystemVerilog support, links to MATLAB and Simulink
VCS AMS updates AMS verification tool and methodology
New data model and optimisation strategy, plus revised analysis engines update Synopsys's IC Compiler place and route tool
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
Uses improved logic optimisations and a new approach to meeting timing.
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
View All Sponsors