Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
IP provides key building blocks for building better video and audio playback devices using HDMI 2.1
Better integration of EM modeling and analysis tools with Synopsys' Custom Compiler should enable tighter design margins
Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.
ARM and Tanner EDA aim to chart a path toward cheaper, easier to realize designs for the embedded and Internet-of-Things markets.
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
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