Product

September 12, 2018

Mentor automates silicon photonics layout

The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
July 30, 2018

Synopsys catalogues AI IP

The rapid growth of interest in machine learning and artificial intelligence has prompted Synopsys to bring all its AI IP together in a microsite and brochure.
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June 20, 2018

DAC 2018 preview: Mentor

Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
May 17, 2018

Synopsys offers ASIL D ready embedded vision IP for ADAS and autonomous vehicle SoCs

Synopsys has extended its range of semiconductor IP for use in advanced driver assistance (ADAS) and autonomous vehicle SoCs with the launch of embedded vision processor blocks that have been given safety enhancements.
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May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
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April 12, 2018

Free formal verification primer offered by Synopsys

Free e-book offers an introduction to formal verification methods for those who may be curious about the technique, or who need to understand its advantages and limitations in order to manage its use effectively.
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April 10, 2018

Control test point counts for ISO 26262

The automotive safety standard targets 90% in-system test coverage. VersaPoint technology helps to simplify reaching your target.
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April 5, 2018

Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
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February 27, 2018

Synopsys UFS 3.0 IP doubles bandwidth to flash

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
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February 13, 2018

HyperLynx update automates SerDes validation

Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
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